Monolithic Active Pixel detector in 0.13 ?m triple well CMOS Technology (A new approach with a full analog signal processor at pixel level and an extended collecting electrode)

1
Monolithic Active Pixel detector in 0.13 ?m
triple well CMOS Technology(A new approach with
a full analog signal processor at pixel level
and an extended collecting electrode)
S. Bettarini1,2, G. Batignani1,2,
M. Carpinelli1,2, G. Calderini1,2, R. Cenci1,2,
F. Forti1,2, M. A. Giorgi1,2, A. Lusiani2,3,
G. Marchiori1,2, F. Morsani2, N. Neri2,
E. Paoloni1,2, M. Rama1,2, G. Rizzo1,2 ,
G. Simi1, J. Walsh2, L. Ratti4,5, V. Speziali4,5,
M. Manghisoni5,6, V. Re5,6, G. Traversi5,6,
L. Bosisio7, G. Giacomini7, L. Lanceri7,
I. Rachevskaia7, L. Vitale7
1Università degli Studi di Pisa, 2INFN Pisa,
3Scuola Normale Superiore di Pisa, 4Università
degli Studi di Pavia, 5INFN Pavia, 6Università
degli Studi di Bergamo, 7INFN Trieste and
Università degli Studi di Trieste
Vertex 2005 - Chuzenji Lake, Nikko -
8 November 2005
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Outline

• Introduction standard CMOS MAPS for tracking in
  HEP
• The new features of our MAPS
• deep n-well collecting electrode
• signal processing at pixel level
• Prototype characterization
• Front-End Electronics
• Sensor response to
• Infrared Laser
• soft X-ray from 55Fe
• b-ray from 90Sr/90Y
• Conclusions

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CMOS MAPS

• Several reasons make them very appealing as
  tracking devices
• detector readout on the same substrate
• wafer can be thinned down to few tens of mm
• radiation hardness (oxide nm thick)
• high functional density and versatility
• low power consumption and fabrication costs

• Principle of standard operation
• The undepleted epitaxial layer acts as a
  potential well for electrons moving by diffusion
• Signal (1000 e-) collected by the
• n-well/p-epi diode
• Charge-to-voltage conversion
• provided by the sensor capacitance
• ? small collecting electrode
• Extremely simple in-pixel readout
• (3 NMOS,PMOS not allowed)
• ? sequential readout

M.I.P.80 e-h pairs /?m
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A new approach to MAPS
In triple-well CMOS processes a deep n-well is
used as a shielding frame against disturbancies
from the substrate to provide N-channel MOSFETs
with better insulation from digital noise

• The new design features of our CMOS pixels
• The deep n-well can be used as the collecting
  electrode
• A full signal processing circuit can be
  implemented at the pixel level overlaying the
  NMOS transistors on the collecting electrode

Use of the deep n-well was proposed by
Turchetta et al. (2004 IEEE NSS Conference
Record, N28-1) to address radiation hardness
issues
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Deep n-well sensor concept (I)

• Standard signal processing chain for capacitive
  detector implemented at pixel level
• Charge-to-Voltage conversion
• done by the charge preamplifier
• The collecting electrode can be
• extended to obtain higher
• single pixel collected charge
• (the gain does NOT depend
• on the sensor capacitance)

DISC
PRE
SHAPER
LATCH
Elementary cell
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Deep n-well sensor concept (II)

• NMOS devices of the analog section built over the
  deep n-well
• Included complementary devices needed for CMOS
  design
• Fill factor ? Area(deep n-well)/Area (total
  n-wells)
• (? 0.85 in the prototype
• test structures)
• Large sensitive element
• crucial to maximize charge
• collection efficiency
• The readout scheme well fits
• into already existent architectures
• for data sparsification at the pixel
• level to improve readout speed

Pixel cell layout
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Device Simulation (ISE-TCAD)

• Detailed physical level simulations performed
  using ISE-TCAD software to
• understand the charge collection mechanism and
  its time properties
• study the influence of other n-wells and the
  neighboring pixels
• optimize sensor design
• (3D simulation needed, in progress)

• Preliminary results
• Single pixel collected charge 1500 e-
• assuming p-epi ? 15 ?m thick
• (likely to be true)
• Charge collection drops rapidly out of deep
  n-well area (te10 ms in the p-epi layer)
• Collection time 50 ns

Uncertainties about the process Test
structure chip realized to measure some process
parameters ? a crucial input for simulation
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Test Chip Layout
0.13 mm CMOS HCMOS9GP by STMicroelectronics
epitaxial, triple well process (available through
CMP, Circuits Multi-Projets)
channel 5 - pixel with input pad for charge
injection (830 mm2 collecting electrode area)
Single devices
channel 6 - pixel with small (830 mm2) collecting
electrode area
channel 4 - pixel with large (2670 mm2)
collecting electrode area
channel 3- pixel with medium (1730 mm2)
collecting electrode area
channel 2 - pixel with input pad for charge
injection (100 fF detector simulating
capacitance)
channel 1 - pixel with input pad for charge
injection
Ch. 1-2-5 have integrated injection capacitance
for readout electronics characterization
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Pixel level charge processor

• High sensitivity charge preamplifier with
  continuous charge reset (n-well/p-epi
  diode leakage current)
• The preamplifier input provides the bias to the
  deep n-well (0.3 V)
• Input device (W/L3/0.35) optimized for a 100 fF
  detector capacitance and operated at a drain
  current of about 1 mA

• RC-CR shaper with programmable peaking time0.5,1
  and 2 ms. Conservatively chosen to avoid
  ballistic deficit
• A threshold discriminator is used to drive a NOR
  latch featuring an external reset
• Power consumption 10 mW

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Front-End Electronics Characterization

• Shaper response to a 560 e- input charge at the
  three different peaking times
• About 15 variation in peak amplitude moving from
  the shortest to the longest peaking time

• Slight overshoot probably due to residual
  parasitic coupling between preamplifier input and
  shaper output
• The latch preserves the signal until it has been
  retrieved
• External reset signal sent to the latch returns
  it to the initial condition

threshold
0
1
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Charge Sensitivity (Gain)
Measured in the three channels with integrated
injection capacitance
CinjCin
CMIMDCinjCin

• Post layout simulations (PLS) within 10 of
  measured gain
• Change in the charge sensitivity probably due to
  loop gain degradation in the charge preamplifier
  (high detector capacitance, small forward gain)

CDCinjCin
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Noise Measurements

• Equivalent Noise Charge is linear with
  CTotCDCFCinjCin
• CD detector capacitance(270fF ch.5,
  CDMIM100fF)
• CF preamplifier feedback capacitance (8 fF)
• Cinj test inj. Capacitance (30 fF)
• Cin preamplifier input capacitance (14 fF)
• Equivalent Noise Charge model

• No significant variation as a function of tp

SWseries white noise spectral density Af1/f
noise power coefficient A1, A2shaping
coefficients
dominant contribution
Noise performance greatly affected by sensor
capacitance actually higher than expected during
the design phase. Direct measurements of
p-epi/deep n-well junction capacitance on test
structures confirm. Great improvement in next
chip submission!
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Response to I.R. laser

• Infrared laser used to emulate charge released
• by a charged particle
• ?1060 nm ? abs. Coefficient10 cm-1 in Si
• Total charge released equivalent to 6 MIPs
• Charge released in a broad region under the
  sensor the fraction of the charge collected by
  the pixel depends on the laser spot profile (not
  well known yet)

• The largest pixel collects the largest charge
• Charge does not scale linearly ? laser spot
  larger than the pixel area and with non uniform
  profile
• Results roughly compatible with a gaussian laser
  spot profile of 50 ?m

Channel no. CD fF Charge sensitivity mV/fC Collected charge e-
3 660 360 1250
4 1280 330 1500
6 270 430 880
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Calibration with soft X-rays from 55Fe

• Peak value of the shaper output
• blue -55Fe source (5.9 keV)
• green - no source
• (same acquisition time)

• X-ray from a 55Fe source used to
• calibrate pixel noise and gain in
• channels with no inj. capacitance

?105 mV ?12 mV
Threshold set cuts this region
5.9 keV line ? 1640 e/h pairs

• charge entirely collected? clear peak _at_ 105 mV ?
  gain400 mV/fC
• charge only partially collected ? below 100 mV
  excess of events w.r.t. noise only spectrum

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Calibration results with 55Fe
Pixel noise distribution
Using gain measured with 55Fe Pixel noise 8 mV
ENC125 e-
mean8mV
Calibration with 55Fe source in good agreement
with results obtained with the inj. capacitance
and within 15 from PLS (Expected ENC150 e-,
gain430 mV/fC)
Signal expected from M.I.P is about 1500 e- (by
sensor simulation with p-epi gt 15 ?m thick,
assuming MIP most probable signal 80 e-/?m)
S/N expected 12
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Response to b-ray from a 90Sr/90Y source
Response to M.I.P from the beta source used to
measure S/N ratio
Electrons from 90Sr and 90Y
15 die in Si
e-
45 are M.I.P Landau peak
Scintillator
Si chip 300 mm
40 release more than a M.I.P, they deform Landau
shape or saturate the shaper
b source
Acquisition triggered by the coincidence
(scintillator AND pixel) signal above threshold,
set _at_ 0.5 MIP
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Results from b-ray

• Peak value of the shaper output
• blue - with b source
• green - no source

• The spectrum clearly shows a Landau peak _at_80 mV
• Using M.I.P signal and average pixel noise
• S/N10
• Using gain measured with 55Fe, M.I.P most
  probable energy loss corresponds to about 1250 e-
  
• Fair agreement with sensor simulation 1500 e-
  expected for p-epi layer thickness gt15 ?m
• Some hint on the process secrets p-epi layer is
  thick!

Landau peak 80 mV
saturation due to low energy particle.
1250
2200
3000 (e-)
Threshold set cuts this region
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First chip successfully tested!

• Results obtained with infrared laser and
  radioactive sources demonstrate the capability of
  the designed sensor to collect and process the
  charge released in the p-epi layer under the deep
  n-well sensitive electrode
• Full functionality sensor readout
  electronics
• Good agreement observed among various results
• Readout calibration with injection capacitance
• Results from Post Layout Simulation
• Response to 55Fe and 90Sr / 90Y sources
• Signal expected from sensor simulation
• The present S/N10 is not outstanding but will be
  improved by about a factor 3 in the next chip
  (going to arrive)
• Input element of the preamplifier must be
  optimized for a more realistic detector
  capacitance (320 fF)
• Noise expected from PLS ENC 50 e- (first chip
  150 e-)

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A deep n-well sensor matrix is coming
(Submitted in August, expected delivery date
mid-November )

• 8x8 matrix (50 mm pitch)
• 5 single pixel channels (different collecting
  electrode area/smaller pixel size)
• (300mm) chips thinned down to
• 150mm
• 100mm
• includes modified version of the charge
  preamplifier to address the noise issue raised by
  the 1st submission prototype
• (still) sequential readout and generation of a
  trigger signal as the logic sum of all of the
  latch outputs

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Conclusions

• New CMOS MAPS detector with analog processing at
  pixel level fabricated in 0.13 ?m triple well
  process
• Extended size of the collecting electrode (deep
  n-well) with respect to the pixel area and part
  of the readout electronics placed over the
  collecting electrode to allow more complex
  processing at the pixel level
• First test chip with single pixels successfully
  tested with infrared laser and radioactive
  sources
• Going to arrive a pixel matrix with sequential
  readout and improved noise performance S/N
  expected 30
• The final goal to develop a matrix with
  sparsified readout suitable to be used in a
  trigger system based on associative memories
• This project has been funded by the Italian
  Ministry for Education, University and Research
  and will be pursued with the new SLIM (Silicon
  detectors with Low Interaction with Material)
  I.N.F.N. collaboration

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Backup slides
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Details on test channels
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Test structure test under way!
P-well max depletion 0.4 mm
p
p
p
n
n
pepi
Breakdown _at_ 10V !
niso
pepi
p-epi max (_at_10V) depletion 3 mm
Diode_niso_pepi