A BiCMOS Synchronous Pulse Discriminator for the LHCb Calorimeter System.

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A BiCMOS Synchronous Pulse Discriminator for the
LHCb Calorimeter System.

1. Introduction.
2. Requirements.
3. System architecture
4. Design of the components
5. Results
6. Conclusions

S. Bota, A. Diéguez, D. Gascón, R. Graciani -
LECC Workshop- September 2002 Colmar
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I. Introduction
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II. Requirements (Energy measurement)
Energy deposition in a SPD cell (electrons and
photons).

• Energy deposition

• Random signal shape (20-30 phe/MIP)
• Shaping methods discarded

Single event MIP signal
Integrate
BW?100 MHz
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II. Requirements (Timing)
Average MIP signal

• Only about 80 of signal in 25 ns
• No dead time on integration
• Response to consecutive events

?d ?12 ns

• Dual channel synchronous system
• Pile-up correction

Normalized integral of Cosmic ray signals in main
and secondary period
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II. Requirements (Other)

• PMT gain limited by aging (DC current) ?
  100fC/MIP in central cells.
• Resolution ? 0.05 MIP (ltlt resolution given by
  photostatistics).
• 5-10 MIP range to perform tail correction.
• Bandwidth gt 100MHz.
• Linearity error lt 5.
• Robust to temperature variations (band gap
  reference).
• Small cavity ? Power consumption lt 1W.

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III. System architecture
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IV. Components (Input stage Preamplifier)
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IV. Components (Input stage Integrator)
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IV. Components (Input stage Noise and Offset)
Transfer function of a system that integrates for
?T?

• Noise

• Offset

Approx. transient response for tltlt
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IV. Components (Pile-up compensation variable Gm)
Common mode offset VbiasDVbiasH-VbiasL
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IV. Components (Pile-up compensation Track
Hold)
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IV. Components (Comparison input stage)
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IV. Components (Comparison latched comparator)
Acquisition
Latch
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IV. Components (DAC)
7 bits floating DAC 1b for sign 6b for
modulus Multiplying R-2R architecture
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V. Results (Introduction)

• Design not tested yet (received last week).
• Results exist for previous versions
• 5V supply
• Gain is 1/3
• Same system architecture
• Same operation principle for the majority of the
  blocks.

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V. Results (Input stage)
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V. Results (Cross coupled transconductor)
Tolerance lt2

• Input common mode range 1V to 0.8V
• Input differential range ?2 V.
• Linearity error lt1
• Bandwidth 100MHz
• Offset ltViogt 5 mV ?Vio6 mV r.m.s.
• Noise voltage (Eno) lt 1 mV r.m.s

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V. Results (DAC)

• INL lt0.6 LSB
• DNL lt0.8 LSB
• Offset lt2 mV
• Settling time 110 ns

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V. Results (Discriminator channel general)

• Offset (Output Zero Error)
• ltOZEgt 35 mV
• ?OZE 63 mV r.m.s.
• Output range is gt?1V
• Linearity error is lt 0.5 full scale.
• Power consumption 140 mW

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V. Results (Discriminator channel noise)

• Conditions to study the sensitivity of a
  discriminator channel to noise and interference
• Different conditions for noise sources (other
  channels)
• ECL and CMOS outputs
• Differential and single ended outputs.
• Switching and fixed output.
• Socket and soldered on PCB
• Combination of pick-up and random noise.
• In any case ?Thresholdlt 1.5 mV r.m.s. (in lab.
  test bench).

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V. Results (Discriminator channel test beam)

• High energy electron signal.
• PMT High Voltage 750 V.
• Threshold 3? above pedestal noise (THlt0.1 MIP).

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VI. Conclusions

• Design of 3.3 V full-custom synchronous
  discriminator.
• Total dose lt 7 Krad (10 year). Protection for
  single event phenomena
• SEU triple voting
• SEL extra guard rings.
• Requirements are fulfilled by previous versions
  (5 V) except for consumption and gain (new
  requirements).
• Functional and radiation tests will be performed
  during autumn and winter.
• Offset could limit the dynamic range of the
  system due to the higher gain of the system.
• External offset cancellation (input bias
  current).
• Programmable offset trimming.

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VI. Conclusions

• 8 ch. Prototype
• Area 30 mm2
• To be submitted after radiation tests.

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IV. Components (Input stage OpAmp)