The CMP Service CMP 46 avenue Flix Viallet 38031 Grenoble Cedex, France http:cmp'imag'fr

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The CMP ServiceCMP46 avenue Félix
Viallet38031 Grenoble Cedex, Francehttp//cmp.i
mag.fr
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• CMP
• 1981
• industrial quality process lines (University
  process lines
• cannot offer a stable yield)
• design kits to link CAD and MPW, to facilitate
  the design.

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• Universities / Research Labs / Industry
• About 650 Institutions in 60 countries
• 19811982 launching CMP with NMOS
• 19831984 development of NMOS, launching
  CMOS
• 19841986 development of CMOS
• 19871989 abandon NMOS, increase the
  frequency of CMOS runs
• 19901994 launching Bipolar, BiCMOS,
  MESFET GaAs, HEMT GaAs, advanced CMOS (.5 µ
  TLM) and MCMs
• 19951997 launching CMOS, BiCMOS and GaAs
  compatible MEMS, DOEs, deep-submicron CMOS
  (.25 µ 6LM)
• 1998 launching surface micromachined MEMS,
  abandon MESFET GaAs
• 1999 launching SiGe, .18 µ CMOS
• 2001 .35µ HBT SiGe BiCMOS, .12µ CMOS,
  SOS/CMOS
• 2003 .25 µ HBT SiGe BiCMOS, InP HBT,
• MEMS PolyMUMPS, SOIMUMPS, MetalMUMPS,

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Summary of services one stop shop ICs
AMS 0.8 µ CMOS BiCMOS DLP/DLM 0.6 µ CMOS
DLP/TLM 0.35 µ CMOS DLP/4LM 0.35 µ
CMOS-Opto DLP/4LM 0.35 µ SiGe BiCMOS
DLP/4LM STMicroelectronics 0.18 µ 0.12 µ CMOS
6LM 0.35 µ SiGe BiCMOS 5LM 0.25 µ SiGeC
BiCMOS 5LM OMMIC 0.2 µ P-HEMT GaAs
PEREGRINE 0.5 µ CMOS SOI/SOS DLP/TLM MEMS
CMOS, BiCMOS and GaAs compatible bulk
micromachining MUMPs from MEMSCAP
CAD Cadence, Tanner, ARM Design
kits 40 kits Packaging standard
packages, customization
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CMOS 0.8 µ CYE austriamicrosystems 2 Levels
Polysilicon, 2 Levels Metal. Mature process for
Analog, Digital, Mixed A/D, and MEMS. Libraries
Digital and Analog Standard Cells Pads
P-Cells. BiCMOS 0.8 µ BYQ austriamicrosystems 2
Levels Polysilicon, 2 Levels Metal. High
Resistive Polysilicon. Vertical Bipolar NPN Ft
12 GHz Analog, Digital, Mixed A/D, RF, and
MEMS. Libraries CMOS, BiCMOS, ECL/CML, RFPADS,
SPIRAL CMOS 0.6 (CUP) austriamicrosystems Met.
layer(s) 3 Poly layer(s) 2 about 250 digital
cells Supply voltage 5V or 3.3V Application
High performance analog/digital process High
resistive poly Mixed signal analog digital, large
digital designs
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CMOS 0.35 µ C35 austriamicrosystems 2 Levels
Polysilicon, 4 Levels Metal, 3.3V / 5.0V, High
Resistive Poly. 3.3V / 5.0V I/O pads. Peripheral
cells with high driving capability (from 1mA to
24mA) Application Analog, Digital, Mixed A/D,
RF. Density 18 kgates/mm2 Gate Delay 100ps
(NAND2 typical) Libraries Digital and Analog
Std Cells Pads SPIRAL Ind.
P-Cells. CMOS-Opto 0.35 µ C35 austriamicrosystems
Provides enhanced optical sensitivity for
embedded photodiodes and high density CMOS camera
products.
SiGe HBT-BiCMOS 0.35 µ S35 austriamicrosystems 4
Levels Polysilicon, and 4 Levels Metal. Power
supply voltage range (2.5V 3.6V / 5.5V)
Vertical SiGe-HBT NPN Ft 70 GHz High resist
Poly, high precision Poly1/Poly2 capac and MIM
capac
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SOI/SOS CMOS from Peregrine
Minimum drawn Length 0.5 µ Operating voltage
1.5 Volt -gt 3.6 Volt Double Layer Polysilicon
(High Resistive Poly Option) Triple Layer
Metal MIM capacitor, and thick Metal3 for
inductors Full-Custom Cadence Design-Kit P-cells
MOS transistors, capacitors, resistors,
inductors Maximum Die Size 18.8mm x 19.13mm 359
mm2
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• P-HEMT E/D GaAs from OMMIC
• ED02AH technology
• Gallium arsenide technology for microwaves
  circuits,
• P-HEMT transistors of 0.2 µ (enhancement
  depletion mode),
• Diodes, resistors, capacitors, spiral inductors,
  air bridges,via holes.
• Typical applications
• Low power low noise circuits for microwaves
  circuits up to 60 GHz
• Low noise amplifier for the L band
• Low power for digital applications with very high
  speed clock
• Analog functions with digital control

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• HCMOS9 0.12µ CMOS from STMicroelectronics
• Gate length .13µ (drawn), .11µ (effective)
• Triple well
• Power supply 1.2 V
• Multiple Vt transistor offering
• (Ultra low leakage, Low leakage, High speed)
• Threshold voltages (for 3 families above)
• VTN 570/500/380 mV,
• VTP 590/480/390 mV
• Isat (for 3 families above)
• TN _at_ 1.2 V 410/535/680 µA/µm
• TP _at_ 1.2 V 170/240/320 µA/µm

HCMOS9 Interconnect cross-section (6 layers
Metal) Courtesy STMicroelectronics
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BiCMOS6G SiGe BiCMOS 0.35 µ
STMicroelectronics Gate length 0.35
micron Single layer Poly / 5 layers Metal MIM
2nF/mm2 High res. Poly 1kOhm/sq Thick Metal
5 2.5 micron Ft 45GHz (Vertical NPN) Nf
0.8dB _at_ 2GHz (Vertical NPN) Standard Power
supplies 3.3V or 5.0V
Cross-section of an SiGe NPN transistor Courtesy
STMicroelectronics
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BiCMOS7RF SiGeC BiCMOS 0.25 µ
STMicroelectronics For RF and Power
Applications Great HF noise figure Reduce
substrate coupling Allow power amplifier
integration Offer high performance passive
devices Increase CMOS density
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• MEMS at CMP
• Portfolio
• Integrated bulk micromachining technologies
• Specific technologies

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Specific technologies

• MEMSCAP PolyMUMPS
• Surface micromachining
• 3 polysilicon levels

poly2
poly1
poly0
Si
Fixed chip size 1cm² Post process Etching,
drying, slicing
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Specific technologies

• MEMSCAP SOIMUMPS
• Micromachining by RIE etching
• SOI substrate

Fixed chip size 1cm²
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Specific technologies

• MEMSCAP MetalMUMPS
• Nickel electroplating thick films
• Bulk and surface micromachining
• Walls metallization

Fixed chip size 1cm²
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Integrated technologies

• CMOS FSBM
• Bulk micromachining austriamicrosystems 0,8 µ
  CMOS et BiCMOS
• Anisotropic etching without additional mask

Integrated technology
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Integrated technologies intégrées

• GaAs FSBM
• Micro-usinage en volume sur OMMIC GaAs
• Gravure anisotrope sans masque additionel

Technologie intégrée
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Packaging Service
CMP offers a Complete Assembly Service
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Packages
Ceramic Packages
Plastic Packages
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Package Guidelines

• Ceramic or Plastic ?
• Prototyping
• CMP recommends to use ceramic packaging
• Advantage Price for small quantities
• Flexible constraint for the
  packaging
• Thermal, High-Reliability
  (Space qualification)
• Prototyping Low volume
• CMP recommends to choose the plastic package and
  then ceramic package
• Advantage Low cost from 30-40 packaging (open
  tool only)
• Access to density solutions
  for low price (LPCC, TAPP)

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Microsystems Packaging Solution

• Standard Solutions
• Ceramic

• Case by case Solutions
• Hybrid
• Chip On Board

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Packaging Process for MPW Run
Ø 17, 25, 33um Wire bonding (Al or Au)
Ceramic Packaging
Packaging
Plastic Packaging
Sawing
Naked Dies on Blue film
Wafer
Ultrasonic Bonding Thermosonic Bonding
Visual Inspection
Loading in Waffle Pack
Waffle Pack
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To be noted

• Conditioning of wafers and naked dies (vacuum or
  nitrogen atmosphere)
• Service for additional packaging from previous
  runs
• Metallic package, hybrid solutions
• Chip-Scale Package

cmp_at_imag.fr
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Design Kits distributed by CMP
40 Design kits
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CAD Tools from CMP
Academia Tanner Leonardo-ModelSim
CADENCE ARM
Academia Tanner Industry
MEMSCAP Tools
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Cooperation CMP ARM
CMP distribute ARM core based tools ARM
Developer Suite Development boards Debug
tools New integration
of ARM cores on ST 0.12 CMOS
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Conclusions. CMP
started in 1981. complete portfolio (ICs, MEMS,
CAD, .). offers the best advanced processes
. Cooperation CMC CMP MOSIS