The CMP Service CMP 46 avenue Flix Viallet 38031 Grenoble Cedex, France http:cmp'imag'fr

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The CMP ServiceCMP46 avenue Félix
Viallet38031 Grenoble Cedex, Francehttp//cmp.i
mag.fr
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Generalities

• 1981
• industrial quality process lines (University
  process lines cannot offer a stable yield)
• design kits to link CAD and MPW, to facilitate
  the design.
• Customer base development
• Universities / Research Labs
• Industry
• 550 Institutions in 60 countries
• Non-profit, non-sponsored

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Technical development

• 19811982 launching CMP with NMOS
• 19831984 development of NMOS, launching
  CMOS
• 19841986 development of CMOS
• 19871989 abandon NMOS, increase the
  frequency of CMOS runs
• 19901994 launching Bipolar, BiCMOS, MESFET
  GaAs, HEMT GaAs, advanced CMOS (.5 µ TLM) and
  MCMs
• 19951997 launching CMOS, BiCMOS and GaAs
  compatible MEMS, DOEs, deep-submicron CMOS
  (.25 µ 6LM)
• 1998 launching surface micromachined MEMS,
  abandon MESFET GaAs
• 1999 launching SiGe, .18 µ CMOS
• 2001 .35 µ HBT SiGe BiCMOS, .12 µ CMOS
• 2003 PolyMUMPS, MetalMUMPS, SOIMUMPS
• 2004 90 nm CMOS, BCD-SOI
• 2005 ASIMPS, SUMMIT/SANDIA

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Summary of services one stop shop
ICs austriamicrosystems 0.6 µ CMOS
DLP/TLM 0.35 µ CMOS
DLP/4LM 0.35 µ CMOS-Opto
DLP/4LM 0.35 µ BiCMOS
DLP/4LM 0.35 µ SiGe
BiCMOS DLP/4LM STMicroelectronics 0.12 µ
CMOS 6LM 90 nm CMOS
8LM 0.35 µ SiGe
BiCMOS 0.25 µ BiCMOS7RF
HBT SiGeC ATMEL BCD
SOI OMMIC 0.2 µ GaAs
HEMT MEMS OMMIC GaAs HEMT
MEMSCAP PolyMUMPs,
SOIMUMPS, METALMUMPS
ASIMPS
CAD Tanner, ARM Design kits for all
technologies and main CAD tools Packaging
standard packages, customization
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austriamicrosystems processes

• CMOS, BiCMOS, SiGe BiCMOS

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BiCMOS 0.8 µ BYQ austriamicrosystems 2 Levels
Polysilicon, 2 Levels Metal. High Resistive
Polysilicon. Vertical Bipolar NPN Ft 12
GHz Analog, Digital, Mixed A/D, RF, and
MEMS. Libraries CMOS, BiCMOS, ECL/CML, RFPADS,
SPIRAL CMOS 0.6 (CUP) austriamicrosystems Met.
layer(s) 3 Poly layer(s) 2 about 250 digital
cells Supply voltage 5V or 3.3V Application
High performance analog/digital process High
resistive poly Mixed signal analog digital, large
digital designs
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CMOS 0.35 µ C35 austriamicrosystems 2 Levels
Polysilicon, 4 Levels Metal, 3.3V / 5.0V, High
Resistive Poly. 3.3V / 5.0V I/O pads. Peripheral
cells with high driving capability (from 1mA to
24mA) Application Analog, Digital, Mixed A/D,
RF. Density 18 kgates/mm2 Gate Delay 100ps
(NAND2 typical) Libraries Digital and Analog
Std Cells Pads SPIRAL Ind.
P-Cells. CMOS-Opto 0.35 µ C35 austriamicrosystems
Provides enhanced optical sensitivity for
embedded photodiodes and high density CMOS camera
products.
SiGe HBT-BiCMOS 0.35 µ S35 austriamicrosystems 4
Levels Polysilicon, and 4 Levels Metal. Power
supply voltage range (2.5V 3.6V / 5.5V)
Vertical SiGe-HBT NPN Ft 70 GHz High resist
Poly, high precision Poly1/Poly2 capac and MIM
capac
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STMicroelectronics processes

• SiGe BiCMOS, CMOS

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BiCMOS6G SiGe BiCMOS 0.35 µ
STMicroelectronics Gate length 0.35
micron Single layer Poly / 5 layers Metal MIM
2nF/mm2 High res. Poly 1kOhm/sq Thick Metal
5 2.5 micron Ft 45GHz (Vertical NPN) Nf
0.8dB _at_ 2GHz (Vertical NPN) Standard Power
supplies 3.3V or 5.0V
Cross-section of an SiGe NPN transistor Courtesy
STMicroelectronics
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BiCMOS7RF SiGeC BiCMOS 0.25 µ
STMicroelectronics For RF and Power
Applications Great HF noise figure Reduce
substrate coupling Allow power amplifier
integration Offer high performance passive
devices Increase CMOS density
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Deep Sub-Micron processes

• 0.18µ, 0.12µ, 90nm CMOS
• From STMicroelectronics

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Feature Size
AMS 0.8µ 1.2k gates/mm2
AMS 0.6µ 3k gates/mm2
ST 0.25µ 35k gates/mm2
AMS 0.35µ 18k gates/mm2
ST 0.18µ 80k gates/mm2
ST 0.12µ 180k gates/mm2
ST 90nm 400k gates/mm2
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HCMOS8D Process Features

• 0.18µ mixed A/D CMOS SLP/6LM
• Gate length (0.18 µm drawn, 0.15 µm effective).
• Shallow trench isolation process.
• Up to 6 levels metal layers with fully stackable
  contacts and vias.
• MIM precision capacitors.
• Thick Metal6.
• Power supply 1.8 V. (Abs. Maximum 1.95 V)
• Threshold voltage VTN 0.5 V, VTP - 0.5 V.
• Ion TN _at_ 1.8 V 500 µA/µm
• Ion TP _at_ 1.8 V 210 µA/µm

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• HCMOS9 0.12µ CMOS from STMicroelectronics
• Gate length .13µ (drawn), .11µ (effective)
• Triple well
• Power supply 1.2 V
• Multiple Vt transistor offering
• (Ultra low leakage, Low leakage, High speed)
• Threshold voltages (for 3 families above)
• VTN 570/500/380 mV,
• VTP 590/480/390 mV
• Isat (for 3 families above)
• TN _at_ 1.2 V 410/535/680 µA/µm
• TP _at_ 1.2 V 170/240/320 µA/µm

HCMOS9 Interconnect cross-section (6 layers
Metal) Courtesy STMicroelectronics
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CMOS090 CMOS 90nm Process Features

• 65nm poly length (90nm drawn)
• Dual Vt MOS transistors
• Dual gate oxide
• Dedicated process flavors for high performance
  or low power
• Dual-damascene copper for interconnect.
• 6 to 9 metal layers for interconnect
• 0.28um metallization pitch.
• Analog / RF capabilities.
• Fully compatible with e-DRAM
• Various power supplies supported 3.3V, 2.5V,
  1.8V, 1.2V, 1V
• Dual standard cell libraries (speed / density)
• (430 kgates/mm2 / 350 kgates/mm2).
• Total of gt 1000 core cells
• Gate delay of 11ps (standard Vt)
• Embedded memories SRAM / ROM / DRAM

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BCD SOI from ATMEL
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BCD-SOI 0.8µ
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P-HEMT GaAs from OMMIC
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• P-HEMT E/D GaAs from OMMIC
• ED02AH technology
• Gallium arsenide technology for microwaves
  circuits,
• P-HEMT transistors of 0.2 µ (enhancement
  depletion mode),
• Diodes, resistors, capacitors, spiral inductors,
  air bridges,via holes.
• Typical applications
• Low power low noise circuits for microwaves
  circuits up to 60 GHz
• Low noise amplifier for the L band
• Low power for digital applications with very high
  speed clock
• Analog functions with digital control

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MEMS Processes at CMP

• Bulk-micromachining
• MUMPS (MEMSCAP)
• ASIMPS (MEMSCAP)
• SUMMiT (Sandia)

new
new
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Bulk micro-machining on Silicon

• CMOS FSBM
• Bulk Micro-machining on the austriamicrosystems
  0,8 µ CMOS BiCMOS
• Anisotropic Etching without additional mask

Compatible with electronics
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Bulk micro-machining on GaAs

• GaAs FSBM
• Bulk Micro-machining on the OMMIC HEMTS GaAs
• Anisotropic Etching without additional mask

Compatible with electronics
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Design-kits for Bulk Micromachining
Bulk-Micromachining Design kit and design-rules
document of the IC process. Add-on for
Bulk-micromachining (layer definitions and
DRC) Additional verifications are made at CMP
with etching simulations.
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MUMPS

• MEMSCAP PolyMUMPS
• Surface micro-machining
• 3 layers polysilicon 1 metal layer

poly2
poly1
poly0
Si
Fixed size 1cm² Post process etching/release,
drying sawing
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MUMPS

• MEMSCAP SOIMUMPS
• RIE etching
• SOI substrate
• 10 to 25 um structure layer
• 2 Metal layers

Fixed size 1cm²
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MUMPS

• MEMSCAP MetalMUMPS
• Thick metal layers electroplating Nickel
  (18-22 um)
• Surface and Bulk Micromachining
• Metallization on the walls

Fixed size 1cm²
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Design-kits for MUMPS

• MEMSCAP technologies
• design kits on CADENCE, TANNER, MENTOR
• Design-kits available for each of the processes
  
• Techfiles
• DRC deck files
• Handbook

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CAD tools for MUMPS

• CAD tools from SoftMEMS (spin-off from MEMSCAP)
• MEMS Xplorer (for UNIX and HP platforms)
• MEMS Pro (for PC platform)

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CMOS MEMS via ASIMPS
ASIMPs CMOS-MEMS Process MEMSCAP, SoftMEMS,
CMU, and Jazz Semiconductor collaboration
Microstructures made from conventional CMOS
followed by two maskless post-CMOS process steps
Potential Applications Inertial sensors, RF
MEMS, infrared sensors, flow and force sensors,
with on-chip detection and conditioning
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Sandia MEMS process SUMMiT V
SUMMiT V Sandia Ultra-planar Multi-level MEMS
Technology V 5 layers poly with planarization.

• Design-kit Available for Autocad 2000
• Design edition and DRC verification
• Design visualization 2D / 3D

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Packaging
CMP offers a complete assembly service

• Ceramic / Plastic
• Prototyping / Low volume
• Wide Range of Packages
• Lead-free Green programs

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Packages
Ceramic Packages
Plastic Packages
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Ceramic Packages
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Plastic Packages Leaded

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Plastic Packages Array, Leadless,Thermal
Thermal Solutions
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Data Sheet (Ceramic Plastic Package)
Available Data to Customers
Blank Bonding Diagram
Mechanical map
Files Extension .pdf, .dwg
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Microsystems Packaging Solution

• Standard Solutions
• Ceramic

• Case by case Solutions
• Hybrid
• Chip On Board

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Design Kits
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Main distributed Design Kits
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CAD Tools from CMP
Academia Tanner Leonardo-ModelSim
CADENCE ARM
Academia Tanner Industry MEMSCAP
(SoftMEMS) Tools
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CAD Tools from CMP
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CAD Tools from CMP Tanner tools
Complete D Kit 0.35 CMOS austriamicrosystems
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IP exploitation
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Austriamicrosystems and STMicroelectronics IP
Blocks

• IP blocks available from CMP for free for Univ.
  Research
• Exemple of requests
• Single Port RAMS
• 128 words of 8 bits
• 128 words of 32 bits
• 2048 words of 8 bits
• 2048 words of 32 bits
• Dual Port RAM
• 256 words of 8 bits

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IP/SoC developments CMP ARM Agreement
CMP is distributor of ARM tools for Universities

• ? ARM suite of tools for programming ARM cores
  ( 500)
• ? Educational kit ( 999)
• ? All other ARM tools
• ? routes to fab for ARM cores
• ? IP providers (under discussion)

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CMP ARM offer integration
0.12 CMOS HCMOS9 Standard CMP runs
STMicroelectronics
ARM 946E-S
Simuation model Abstract view
Several projects in progress
Confidentiality Agreement
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Test

• number pads
• clock frequency
• number of test vectors
• etc.
• Percentage analog/digital

On request, from the user specifications

• SERMA Technologies, France
• LCIE, France
• BULL, France
• CSEE, Switzerland
• austriamicrosystems, Austria
• NNTTF, Australia

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Present cooperative effortsCMC, CMP, MOSIS

• Why?
• To better serve the customer base by providing
  access to a larger technology selection.
• How
• Share the cost of expensive and/or unique
  processes with limited customer base
• Combine submitted designs into a common run,
  operated by one of the partners
• If technologies are accessed by the individual
  groups, the customer base may be too small to
  support the technology, whereas combining the
  customers from all groups may be adequate to
  support the technology in question.
• Expand the IP basis when technologies are
  shared in view of SoC/SIP design.

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. CMP started in
1981. Complete portfolio (ICs, MEMS, CAD, .).
Offers the best advanced processes
Conclusions

• . Cooperation CMC CMP MOSIS
• Quality of Service CMP applies ISO 9002
  standards