Priority encoder

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Priority encoder
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Overview

• Priority encoder- theoretic view
• Other implementations
• The chosen implementation- simulations
• Calculations and comparisons

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The target of the project

• Building priority encoder using the multilevel
  lookahead and folding techniques

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Uses of priority encoding

• INR - interconnection network router
• design of SAE sequential address encoder of a
  content associate memory (CAM)
• microcontroller and microprocessor
• (incrementer / decrementer)

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basic concepts of priority encoders

• The i-th output bit EPi Di Pi
• Di- the input data
• Pi- the priority token passed into this bit
• the relationship between Pi and Pi-1
• Pi Di-1 Pi-1
• the generated EPi is
• EPi Di Di-1 Di-2 D1 D0
  

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Different implementations

• For 4 bit priority encoder

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matrix
Sum of minterms, the straight-forward
implementation

• Because of a minimal distance needed between the
  lines the layout is large and complicated.

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Basic units

• The structure is build from equal units. Each
  unit calculates yi and xpi for the i-th bit

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• Then, by chaining the units we construct the
  output

In this implementation we save silicon area, but
pay in propagation delay
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tree

• Tree of multiplexers implemented by butterflies
• Efficient implementation in area and power, has
  longer propagation
• then the folding technique

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the multilevel lookahead structure

• The output third-level lookahead signal of the
  ith 8-bit macro is
• LA3ii0n-1 D8i7 D8i6 D8i5 D8i4
  D8i3 D8i2 D8i1 D8i LA3i-1
• LA3-1 0
• n N/8
• N number of input bits
• The ith 4-bit sub macros
• LA2i D8i3D8i2D8i1D8iLA3i-1

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The 8-bit macro formulas

• EP8i D8i LA3i-1
• EP8i1 D8i1 D8i LA3i-1
• EP8i2 D8i2 D8i1 D8i LA3i-1
• EP8i3 D8i3 D8i2 D8i1 D8i LA3i-1
• EP8i4 D8i4 LA2i
• EP8i5 D8i5 D8i4 LA2i
• EP8i6 D8i6 D8i5 D8i4 LA2i
• EP8i7 D8i7 D8i6 D8i5 D8i4 LA2i

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8-bit macro cell
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Diagram of 32-bit chain designed encoder
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The folding technique-first level folding

• The LA3i that generated by the macro with the
  higher priority can be connected to other macros
  with lower priority.
• Such connection can make the critical path
  shorter
• In this connection well lose the advantage in
  layout arrangement and wiring complexity

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Folding - implementation

• Well connect LA30 to the second and the fourth
  macros (not to the third) and well get 2x2
  matrix
• in this way the fourth macro is connected to 2
  neighboring macros
• the number of gate delays is reduced to 4
  (ltlog232 )

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Block diagram of a 32-bit priority encoder with
folding
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64 bit priority encoder with first level folding
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Multilevel folding

• In order to reduce the gate delay to be less then
  log2N in grater priority encoders, we can apply
  the folding technique again again for example
• N128
• First-Level folding 8 gate delay
• Second-Level folding 7 gate delay
• Third-Level folding lt7 gate delay

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64-bit priority encoder with 2 levels of folding
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• For 256-bit priority encoder the new design can
  achieve about 10 times performance while spending
  ½ power consumption.

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The implementation

• We decided to implement the project using bottom
  up architecture, starting with a 1 bit unit.
• Each stage will be checked separately.
• Moving to the next stage is only after the
  previous stage is finished

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1 bit unit

• At first we implemented 1 bit unit and checked
  it.
• The circuit

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The simulation
The output
Lookahead bit
The input
The clock
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The 4 bit unit

• The 4 bit unit circuit

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The input signals
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The outputs
Lookahead
When the lookahead high all the outputs equals
zero
outputs
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The 8-bit unit
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The output signals
v3
Not valid
v0
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The next lookahead
v7
v4
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The 32-bit chain encoder
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The results
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The problem we encountered
glitches
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The glitch
the glitch starts after clock rising
clock rising
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The widest glitch comes at higher bits
clock
Bit 60
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32 bit-folding
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64 bit first level folding
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64 bit second level folding
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64 bit second level folding with one critical
path
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Propagation delay - reduction

• To minimize the propagation delay of the EP
• we made the following changes
• Reduced the clock period from 200ns to 20ns.
• Divide the clock pulse to different periods for
  low time and high time.
• Those changes made under the constrains of
• Keeping the high pulse length 80 of the base
  pulse.
• Making sure all the requested changes and
  currents are stable before clock raising.
• The optimum result we conclude for the clock
  period 5ns for low time and 15ns high time.

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Results 32 bit
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Results 64 bit
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Results 64 bit (high)
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80 high pulse
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The vhdl simulation
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The vhdl simulation of a 32 bit priority encoder
Here the lsb of input changes from 0 to 1, and
the output changes
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Compare table
unit matrix tree folding
Area mm² 0.076 0.076 0.043 0.053
Power 10-11fw 149.6 173.4 112.8 127.5
Time ns 241.2 75 18 8
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