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Combinational Logic: Other Gate Types

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Title: 02-Combinational_Logic_1 Last modified by: walid Created Date: 12/9/2002 3:09:50 PM Document presentation format: On-screen Show (4:3) Other titles – PowerPoint PPT presentation

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Title: Combinational Logic: Other Gate Types


1
Combinational Logic Other Gate Types
2
Gate classifications
  • Primitive gate - a gate that can be described
    using a single primitive operation type (AND or
    OR) plus an optional inversion(s).
  • Complex gate - a gate that requires more than one
    primitive operation type for its description

3
primitive gates
  • NAND
  • NOR

4
NAND Gates
5
NOR
  • NOT OR
  • Also common

6
NAND is Universal
  • Universal gate Can express any Boolean
    Function using only this type of gate
  • Equivalents below

7
Sum of Products with NAND
  • Easy to think of bubbles as canceling

8
AND-OR Circuit Easy to Convert
9
NOR Also Universal
  • Dual of NAND

10
Buffer
  • No inversion
  • No change, except in power or voltage
  • Used to enable driving more inputs

11
Parity Function
  • How does parity work ?
  • Given 7- bit ASCII code for A (100 0001)
  • What is the ASCII code for A with even parity ?
  • Write truth table for two input even parity
    generator
  • What needs to be generated for parity bit?
  • What function of two inputs gives you this?
  • This is called Exclusive OR function

12
Example Complex Digital Logic Gates Exclusive
OR/ Exclusive NOR
  • The Exclusive OR (XOR) function is defined as
  • The eXclusive NOR (XNOR) function, otherwise
    known as equivalence is

13
Symbols For XOR and XNOR
  • XOR symbol
  • XNOR symbol
  • Symbols exist only for two inputs

14
Truth Tables for XOR/XNOR
  • Operator Rules XOR XNOR
  • The XOR function means
  • X OR Y, but NOT BOTH
  • Why is the XNOR function also known as the
    equivalence function, denoted by the operator ??

15
XOR Implementations
  • The simple SOP implementation uses the following
    structure
  • A NAND only implementation is

X
Y

X
Y
16
XOR/XNOR (Continued)
  • The XOR function can be extended to 3 or more
    variables. For more than 2 variables, it is
    called an odd function or modulo 2 sum (Mod 2
    sum), not an XOR
  • The complement of the odd function is the even
    function.
  • The XOR identities





Å
Å


17
Question
  • Draw the K-map of a 4 variable odd function

18
Example Odd Function Implementation
  • Design a 3-input odd function F X Y
    Zwith 2-input XOR gates

19
Example Odd Function Implementation
  • Design a 3-input odd function F X Y
    Zwith 2-input XOR gates
  • Factoring, F (X Y) Z

20
Example Odd Function Implementation
  • Design a 3-input odd function F X Y
    Zwith 2-input XOR gates
  • Factoring, F (X Y) Z
  • The circuit

21
Example Odd Function Implementation
  • Design a 3-input odd function F X Y
    Zwith 2-input XOR gates
  • Factoring, F (X Y) Z
  • The circuit
  • Based on the above, given (X,Y,Z,F), then F would
    be the even parity bit for the three bits X,Y,Z.
    Hence, the circuit is an even parity generator.

22
Even Parity Generators and Checkers
  • An even parity bit could be added to n-bit code
    to produce an n 1 bit code
  • Use an odd function to produce codes with even
    parity
  • Use odd function circuit to check code words with
    even parity
  • Example n 3. Generate even parity code words
    of length 4 withan odd function circuit (parity
    generator)
  • Check even parity code words of length 4 with
    odd function circuit
  • Operation (X,Y,Z) (0,0,1) gives(X,Y,Z,P)
    (0,0,1,1) and E 0.If Y changes from 0 to 1
    betweengenerator and checker, then E 1
    indicates an error.

23
Odd Parity Generators and Checkers
  • Similarly, an odd parity bit could be added to
    n-bit code to produce an n 1 bit code
  • Use an even function to produce codes with odd
    parity
  • Use even function circuit to check code words
    with odd parity

24
Tri-State
  • Output w/ 3 states H, L, and Hi-Z
  • High impedance
  • Behaves like no output connection if in Hi-Z (Hi
    Impedance) state
  • Allows connecting multiple outputs

25
Data Selection
  • If s 0, OL IN0, else OL IN1

26
Data Selection Function Implementation with
3-State Logic
  • Data Selection Function If s 0, OL IN0, else
    OL IN1
  • Performing data selection with 3-state buffers
  • Since EN0 S and EN1 S, one of the two buffer
    outputs is always Hi-Z plus the last row of the
    table never occurs.

EN0 IN0 EN1 IN1 OL
0 X 1 0 0
0 X 1 1 1
1 0 0 X 0
1 1 0 X 1
0 X 0 X X
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