InP Bipolar Transistors: High Speed Circuits and Manufacturable Submicron Fabrication Processes

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InP Bipolar Transistors High Speed Circuits and
Manufacturable Submicron Fabrication Processes
2003 European GaAs IC Conference, Munich, October
M. Rodwell, D. Scott, M. Urteaga, M. Dahlström,
Z. Griffith, Y. Wei, N. Parthasarathy, Y-M
Kim, University of California, Santa
Barbara M. Urteaga, R. Pierson , P. Rowell, B.
Brar Rockwell Scientific Company
rodwell_at_ece.ucsb.edu 805-893-3244, 805-893-5705
fax
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Applications of InP HBTs
Optical Fiber Transceivers 40 Gb/s InP and SiGe
HBT both feasible ICs now available market has
vanished 80 160 Gb/s may come in time within
feasibility for scaled InP HBT
mmWave Transmission 65-80 GHz, 120-160 GHz,
220-300 GHz LinksLow atmospheric attenuation
(weather permitting).High antenna gains (short
wavelengths). 10 Gb/s transmission over 500
meters with 20 cm antennas needs 4 mW transmitter
power
Mixed-Signal ICs for Military Radar/Comms
direct digital frequency synthesis, ADCs,
DACshigh resolution at very high bandwidths
sought
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Motivation for InP HBTs
Parameter InP/InGaAs Si/SiGe benefit
(simplified) collector electron velocity 3E7
cm/s 1E7 cm/s lower tc , higher Jbase electron
diffusivity 40 cm2/s 2-4 cm2/s lower tbbase
sheet resistivity 500 Ohm 5000 Ohm lower
Rbbcomparable breakdown fields Consequences, if
comparable scaling parasitic reduction 31
higher bandwidth at a given scaling
generation31 higher breakdown at a given
bandwidth Problem for InP SiGe has much better
scaling parasitic reduction Technology
comparison todayProduction SiGe and InP have
comparable speedSiGe has much higher integration
scales Our Present Efforts Development of
low-parasitic, highly-scaled, high-yield
fabrication processes
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Scaling
Required transistor design changes required to
double transistor bandwidth
key device parameter required change
collector depletion layer thickness decrease 21
base thickness decrease 0.7071
emitter junction width decrease 41
collector junction width decrease 41
emitter resistance per unit emitter area decrease 41
current density increase 41
base contact resistivity (if contacts lie above collector junction) decrease 41
base contact resistivity (if contacts do not lie above collector junction) unchanged
(C s, t s, C/I s all reduced 21)
easily derived from geometry / resistivity /
velocity relationships
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Optical Transmitters / Receivers are Mixed-Signal
ICs
MUX/CMU DMUX/CDR mostly digital
TIA small-signal
LIA often limiting
Small-signal cutoff frequencies (ft , fmax) are
predictive of analog speedLimiting and digital
speed much more strongly determined by I/C ratios
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Design HBTs for low gate delay, not for high ft
fmax !
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Scaling Laws, Collector Current Density, Ccb
charging time
GaAsSb base
InGaAs base
Collector Depletion Layer Collapse
Collector Field Collapse (Kirk Effect)
Collector capacitance charging time is reduced
by thinning the collector while increasing
current
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Technology Roadmaps for 40 / 80 / 160 Gb/s
Scaling Challenges
Loss of yield at small dimensions
emitter
progressively harder to obtain
base
progressively harder to obtain alternative is to
decouple base collector dimensions
decreasing breakdown
collector
heating, thermal resistance
key figures of merit for logic speed
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Deep Submicron Bipolar Transistors for 140-220
GHz Amplification
raw 0.3 mm transistor high power gain _at_ 200 GHz
1-transistor amplifier 6.3dB _at_ 175 GHz
3-transistor amplifier 8 dB _at_ 195 GHz
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M Dahlström (UCSB/ONR) Fang,Lubyshev,
Fastenau,. Liu (IQE)
InP-collector DHBTs Self-Aligned Mesa Structure
0.7 um base contact width 0.5 um
base contact width
200 nm InP collector, 30 nm InGaAs base 8(1019)
/cm3 base doping 1 mm base contacts, 0.5 mm x
7.5 mm emitter junction 0.7 mm emitter contact
Collector / Emitter Ratio 2.0 um / 0.5 um,
1.2 um / 0.5 um
Vce1.7 V J3.7E5 A/cm2
Vbr,ceo7 V
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InP DHBTs 150 nm collector, 30 nm base
Dahlström, Griffith(UCSB/ONR) Fang,Lubyshev,
Fastenau, Liu (IQE)
Ccb/Ic ? 0.26 ps/V
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Z. Griffith, M Dahlström
Mesa DHBT with 0.6 mm emitter width, 0.5 mm base
contact width
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75 GHz, 80 mW Power Amplifier
Y. Wei
0.4 ? 0.9 mm die, AE 16 x (1mm x 16 mm)
256 mm2 transferred-substrate process
Bias Ic130 mA, Vce4.5 V
250-500 mW is feasible UCSB designs are
constrained by yield difficulties with large of
fingers
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87 GHz HBT static frequency divider
PK Sundararajan
InAlAs /InGaAs/InP MESA DHBT 400 Å base, 2000 Å
collector, 9 V BVCEO 200 GHz ft, 180 GHz
fmax 2.5 x 105 A/cm2 operation
We are now designing for 150 GHz...
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UCSB/ONR PK Sundararajan
8 GHz S-D ADC
Technology0.7 um InP MESA DHBT 400 Å base, 2000
Å collector, 9 V BVCEO, 200 GHz ft, 180 GHz
fmax2.5 x 105 A/cm2 operation
Design simple 2nd-order gm-C topology comparator
is 87 GHz MSS latch integration by capacitive
loads 3-stage comparator, RTZ gated DAC
Results133 dB (1 Hz) SNR at 74 MHzequivalent to
8.8 bits at 200 MS/s
975 kHz FFT bin size 8 GHz clock rate 65.5 MHz
signal641 oversampling ratio
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OC-768 Modulator Driver
K. Krishnamurti et al
Design Issues Gain flatness Distributed line
losses, current handling loaded Z0 Complexity
of transmission-line layout Associated
low-frequency droopEmitter follower negative
resistance ? peaking Efficacy of bypass
capacitances Common-mode traveling-wave
instability
30 dB gain, 40 GHz bandwidth, gt10 dB S11 S22
8 ps rise/fall (20-80) , 0.9 ps RMS jitter 3
Vpp single ended output, 6 V differential
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InP HBT limits to yield non-planar process
Failure modes
Emitter contact
Etch to base
Liftoff base metal
Emitter planarization, interconnects
Yield quickly degrades as emitters are scaled to
submicron dimensions
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Parasitic Reduction
At a given scaling generation, intelligent choice
of device geometry reduces extrinsic parasitics
wide emitter contact low resistance narrow
emitter junction scaling (low Rbb/Ae)
thick extrinsic base low resistance thin
intrinsic base low transit time
wide base contacts low resistancenarrow
collector junction low capacitance
Much more fully developed in Si
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Very strong features of SiGe-bipolar transistors
High current density 10 mA/mm2 T-shaped
polysilicon emitter 0.25 mm junction
wide contact low resistance, high yield Thin
intrinsic base low tb Thick extrinsic base low
Rbb Low Ccb collector junction collector
pedestal CVD/CMP SiO2 planarization
regrown poly extrinsic base High-yield, planar
processing high levels of integration
LSI and VLSI capabilities



SiGe clock rates up to 65 GHzMuch more complex
ICs than feasible in InP HBTInP HBT must reach
higher integration scales or will cease to compete
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ManufacturableDeep SubmicronInP HBTs
Planar HBT Dielectric Sidewall Process
Objective speed extrinsic parasitic
reductiondeep submicron scaling Objective
yield planar processeliminate liftoffeliminate
undercut etches Target Applications High speed
(100-200 GHz clock) digital mixed signal.
160 Gb/s optical fiber transmission
Polycrystalline-Emitter (SiGe-like) HBT
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Submicron Sidewall-Spacer (S3) Process
Urteaga Rodwell UCSB Urteaga, Pierson, Rowell
Brar RSC Nguyen Nguyen, GCS
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S3 InP Emitter Focused-Ion-Beam Images
Urteaga, Rodwell , Pierson, Rowell , Brar,
Nguyen, Nguyen UCSB, RSC, GCS
sidewall
emittermetal
W basecontact
emitter
base
emitter
collector
base
base
collector
sidewall
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S3 HBT DC Performance
Urteaga, Rodwell , Pierson, Rowell , Brar,
Nguyen, Nguyen UCSB, RSC, GCS
Low-leakage submicron device Si3N4 passivation
effective base-emitter ledge Large base
ideality factordue to base-emitter grade design
not dielectric passivation
nb 1.6, nc 1.0
b50
S3 HBT with base pad trench
Emitter Area 0.7 x 6 um2
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S3 HBT RF Performance
Urteaga, Rodwell , Pierson, Rowell , Brar,
Nguyen, Nguyen UCSB, RSC, GCS
Base contact 0.5 µm on each side of emitterfmax
limited by high base contact resistance (now
being addressed) High current operation and low
Ccb
Emitter Junction Dimensions JE mA/mm2 Ft GHz Fmax GHz Ccb/IE ps/V
0.4 x 3 mm2 6.0 239 142 0.82
0.4 x 6 mm2 6.8 257 146 0.66
0.6 x 3 mm2 6.7 244 127 0.50
0.6 x 6 mm2 6.9 266 133 0.40
Measurements taken at VCB 0.4 V
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Polycrystalline-extrinsic-emitter regrowth InP
HBT
D. Scott, Y. Wei
Objectives Eliminate emitter undercut
etch Eliminate base-emitter metal
liftoff Flared emitter ? low resistance Thick,
2E20-doped extrinsic base ? low
resistance ? tolerant of contact metal
migration Thin, 3E19-doped intrinsic base
? low transit time ? high current gain
(less Auger recombination)
Polycrystalline InAs -has low resistivity
(2.51 higher than 1019 /cm3 lattice-matched
InGaAs) -can play same role in InP as
the polysilicon emitter in Si/SiGe
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D. Scott, Y. Wei
Poly-extrinsic -emitter regrowth InP HBT
Dennis Scott, Yun Wei UCSB
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Polycrystalline-extrinsic-emitter regrowth HBT
0.5 x 8 um device
D. Scott, Y. Wei
Base plug
emitter
polyimide
collector
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Polycrystalline-extrinsic-emitter regrowth HBT
0.3 x 8 um device
device without self-aligned refractory base
contacts
D. Scott, Y. Wei
Extrinsic emitter
Base contact
Collector contact
Extrinsic Base
0.3 um Intrinsic emitter
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Polycrystalline-extrinsic-emitter regrowth HBTs
D. Scott, Y. Wei
with self-aligned refractory base contacts
without self-aligned refractory base contacts
Issues being addressed leaky base-emitter
junctions surface damaged by processbase
resistance very high hydrogen passivation
of carbon dopingmoderately high emitter
resistance
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Ccb reduction by Collector Pedestal Implant
Yingda Dong
1) Expitaxial growth, pattern with SiN mask,
and Ion implanted with Si
2) N doped pedestal formed
Si Ion Implantation
2000?
?
3) Collector and base regrowth
4) Process for emitter regrowth
?
The extrinsic base-collector capacitance can be
reduced by a factor of three. Pedestal Ccb
reduction can be incorporated into mesa,
sidewall, and emitter regrowth processes
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InP Mesa DHBT with Collector Pedestal Implant
Yingda Dong
Present Status No increase in junction leakage
...good DC characteristicsFull Ccb reduction
not being obtained interfacial charge at
regrowth interface ...now being reduced
400 kA/cm2
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Indium Phosphide HBTs
Millimeter-Wave Power InP a leading contender
unsurpassed combination of bandwidth and
breakdown power amplifiers at 75-110 GHz,
140-220 GHz, beyond Mixed-Signal and Fiber ICs
InP struggling to compete with SiGe
application demands transistor counts near/beyond
yield limits large emitter junctions? high
current ? power near acceptable limits speed
advantage from materials being squandered by
inadequate scaling Critically needed for InP HBT
mixed-signal ICs highly scaled process 0.2
mm emitters, 0.4 mm collectors highly planar
and high-yield fabrication processes small
emitter junctions (0.2 mm x 0.5 mm) for
acceptable power Present efforts in InP research
community low-parasitic, highly-scaled,
high-yield fabrication processes ? 31
higher bandwidth at a given scaling generation
? 31 higher breakdown at a given bandwidth
Substantial risk of failure, substantial benefit
if successful.
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in case of questions
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What HBT parameters determine logic speed ?
Caveats assumes a specific UCSB InP HBT in
development for 250 GHz target clock rate (0.3
um emitter width, 0.6 um wide collector of 150 nm
thickness, 300 Å base thickness, 5E5 A/cm2)
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Why isn't basecollector transit time so
important ?
Depletion capacitances present over full voltage
swing, no large-signal reduction