Firmware-only Implementation of Time-to-digital Converter (TDC) in Field-programmable Gate Array (FPGA)

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Firmware-only Implementation of Time-to-digital
Converter (TDC) in Field-programmable Gate Array
(FPGA)

• Jinyuan Wu, Z. Shi and I. Wang
• For CKM Collaboration
• IEEE NSS 2003, Portland, OR
• Oct. 2003

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TDC Using FPGA Logic Chain Delay

• This scheme uses current FPGA technology ?
• Low cost chip family can be used. (e.g.
  EP1K10QC208-2 15.25) ?
• Fine TDC precision can be implemented in slow
  devices (e.g., 0.4 ns in a 200 MHz chip). ?

IN
Weve done this 10 years ago. There are many
problems
CLK
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Problem 1 Logic Cell Delay Time Difference

• The FPGA compiler can put logic cells anywhere.
  -- The logic path is not easy to predict. ?.
• Delay times in different logic paths are
  different. ?.
• Is hand placement a solution?
• Hand placement is very time consuming. ?.

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Tired of Hand Placement? ?Use Existing Chains! ?
Chain structures exist in FPGAs.
Delay Chain Altera cascade chain
When the 1st LE is placed, there is only one
possible configuration for the remaining LEs
Register Array
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After Compiling Automatically
Delay Chain and Register Arrays For 2 TDCs (48
steps each)
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The Board and the Chip

• Chip Altera ACEX, EP1K10QC208-1 (22.50).
• Clock 35 MHz external, 70 MHz inside the chip.
• Typical precision 0.4 ns/LSB. (This is too good.
  Only 1 ns/LSB is needed. The chip is too fast).

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TDC Count v.s. Input Time

• TDC chains are implemented in 12 possible
  positions in the chip.
• Differences among them are small.

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Short-term Stability

• More than 1000 measurements per point are made.
• Both mean and standard deviation are recorded.
• Measured standard deviation can be explained with
  binning model.
• Intrinsic short-term instability, if there is
  any, ltlt 0.5 LSB.

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Problem 2 Delay Time Change With Temperature

• Delay time changes with temperature and power
  supply voltage.
• In DESER or ASIC, the delay time of the delay
  chain is compensated by adjusting relevant
  voltages. Analog compensation.
• In FPGA, digital compensation is needed.
• Digital compensation uses delay speed measured in
  the same delay chain to correct the arrival time
  of a hit.

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Delay Chain Digital Compensation

• Use longer delay line.
• Some signals may be registered twice at two
  consecutive clock edges.

IN
N2-N1(1/f)/Dt

• The two measurements can be used
• to calibrate the delay.
• to reduce digitization errors.

CLK
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Digital Compensation
2nd TDC

• Power supply voltage changes from 2.5 V to 1.8 V,
  (about the same as 100 oC to 0 oC).
• Delay speed changes by 30.
• The difference of the two TDC numbers reflects
  delay speed.

Corrected Time

• The corrected time variation is less than 1 LSB.

1st TDC
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Problem 3 Bin Width Variation

• The logic cell structure is not perfectly
  uniform.
• Using existing chain helps to improve uniformity.
• Even using existing chain, TDC bins may still
  have different widths.

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Measured TDC Bin Width Variation

• More than 50,000 samples with random arrival time
  for each of 12 chain locations are measured.
• Relative bin width is calculated from number of
  events for each TDC bin.

• Bin-by-bin calibration is possible.
• Its also tolerable without bin-by-bin
  calibration.

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Performance
Measurement Errors (ns) Measurement Errors (ns)
(max) (rms)
Test TDC 0.4-ns-LSB With digital temperature compensation only 0.6 0.2
Perfect 1.2-ns-LSB TDC 0.6
Perfect 0.7-ns-LSB TDC 0.2
Test TDC 0.4-ns-LSB With bin-by-bin calibration 0.3 0.13
Perfect 0.6-ns-LSB TDC 0.3
Perfect 0.45-ns-LSB TDC 0.13
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Summary
Problem 1 hand placement. Use existing chain to avoid hand placement.
Problem 2 temperature variation. Make digital compensation.
Problem 3 bin width variation. Use bin-by-bin calibration. It is also tolerable without.
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The End

• Thanks

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TDC Solutions

• ASIC good for large total system channel count.
• FPGA with DESER good for large channel count per
  package. (CYP15G04K100V1MGC 285.)
• Other situations? Consider low cost FPGA.

Tot sys ch.
Ch/pkg