High-Speed Digital Circuit Design

1
High-Speed Digital Circuit Design
Chris Allen (callen_at_eecs.ku.edu) Course website
URL people.eecs.ku.edu/callen/713/EECS713.htm
2
Outline

• Syllabus
• Instructor information, course description,
  prerequisites
• Textbook, reference books, grading, course
  outline
• Preliminary schedule
• Introductions
• What to expect
• First assignment
• Review of circuit fundamentals
• When are HSD design techniques needed?
• Transient response of reactive circuits
• Measuring device reactance
• Impact of via inductance
• Crosstalk from mutual reactance

3
Syllabus

• Prof. Chris Allen
• Ph.D. in Electrical Engineering from KU 1984
• 10 years industry experience
• Sandia National Labs, Albuquerque, NM
• AlliedSignal, Kansas City Plant, Kansas City, MO
• Phone [phone]
• Email callen_at_eecs.ku.edu
• Office 3024 Eaton Hall
• Office hours TR 4 to 5 PM, MWF 1 to 2 PM
• Course description
• Basic concepts and techniques in the design and
  analysis of high-frequency digital and analog
  circuits. Topics include transmission lines,
  ground and power planes, layer stacking,
  substrate materials, terminations, vias,
  component issues, clock distribution, cross-talk,
  filtering and decoupling, shielding, signal
  launching.

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Syllabus

• Prerequisites
• Electronic Circuits I (EECS 312) Non-linear
  circuit elements, MOSFETs, BJTs, diodes, digital
  circuits and logic gates
• Electromagnetics II (EECS 420) (recommended)
  transmission line theory
• Textbook
• High-Speed Digital Design
• by H. W. Johnson and M. Graham
• PTR Prentice-Hall, 1993, ISBN 0133957241

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Syllabus

• Reference books
• High-Speed Digital Propagation Advanced
  Black Magic by H. W. Johnson and M.
  GrahamPrentice Hall PTR , 2003, ISBN 013084408X
• High-Speed Digital System Design A
  Handbook of Interconnect Theory and Design
  Practices by S. H. Hall, G. W. Hall, J. A.
  McCallWiley-IEEE Press, 2000, ISBN 0471360902
• Digital Transmission Lines Computer
  Modeling and Analysisby K. D. GranzowOxford
  University Press, 1998, ISBN 019511292X

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Grades and course policies

• The following factors will be used to arrive at
  the final course grade
• Homework quizzes 15 Design project 15
  Midterm exam 35 Final exam 35

Grades will be assigned to the following
scale A 90 - 100 B 80 - 89 C 70 - 79
D 60 - 69 F lt 60 These are guaranteed
maximum scales and may be revised downward at the
instructor's discretion. Read the policies
regarding homework, exams, ethics, and plagiarism.
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Outline and schedule

• Tentative Course Outline (subject to change)
• Review of circuits, electronics and traveling
  wave theory(Thevenin and Norton equivalents,
  device capacitance and inductance, current
  sourcing and sinking transmission line impedance,
  source and load impedance, reflections)
• Measurement Issues(requirements and
  specifications, design for test, test equipment,
  special fixtures)
• Properties of high-speed gates(circuit families
  and their characteristics, propagation delay,
  rise/fall times, input impedance, output
  impedance, sensitivity to electro-static
  discharge (ESD), heat dissipation)
• Transmission lines(microstrip, stripline,
  coplanar, multiwire)
• Ground and power planes(number of planes,
  placement, characteristics)
• Substrate materials(printed wiring boards
  (PWBs), multi-chip modules (MCMs))
• Thermal issues(junction temperature, thermal
  resistance, thermal vias, cooling options)
• Packaging technologies(packaged parts on PWB
  (through hole and surface mount), bare die,
  chip-on-board, multi-chip modules)

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Outline and schedule

• Tentative Course Outline (continued)
• Routing issues(fanout limits, stubs, daisy
  chaining, testability)
• Terminations and vias(termination options)
• Clock distribution(timing skew, fanout, fine
  adjustments)
• Cross-talk(analysis, design rules, consequences)
• Filtering and decoupling(techniques and
  requirements)
• Shielding and grounding(electromagnetic
  interference (EMI) and electromagnetic
  compatibility (EMC))
• Signal launching(connection between boards,
  impedance matching)
• Special high-speed circuit design
  techniques(pipelining and latency, multiplexing)
• Future trends(chip speed, complexity, number of
  I/O, optical interconnection (die and board
  level), chip stacking)

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Overview

• Many of the topics discussed are covered
  adequately in the text
• Other topics to be discussed will use additional
  resources including manufacturers application
  notes, product data sheets, and other texts.
• High-frequency circuit design is both an art and
  a sciencehence the Black Magic reference in the
  title.
• The text presents general design rules frequently
  without deriving themthese result from past
  experience and were learned the hard way.
• What is meant by high frequency or high
  speed?These are relative terms.What we mean is
  typically signals with fundamental frequency
  components gt 100 MHz although lower frequency
  signals may qualify in some cases.

10
Applications

• Numerous systems use high-speed digital
  signals.Examples include
• Radar systemsGSa/s analog-to-digital converters
  (ADCs) and digital-to-analog converters (DACs)
  systems with wide signal bandwidths computations
  measured in GFLOPS
• Communication systemschannel rates of 40 Gb/s
  are common today over long-distance optical fiber
• Computerssupercomputers and cluster computing
  performance measured in operations per second
  (OPS) fine-resolution displays

Giga-sample per second GSa/s Giga-bit per
second Gb/s Giga-floating operations per
second GFLOPS
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Applications

• Many of the high-speed digital design techniques
  apply to both analog and digital signals.
  Examples include passive component selection and
  interconnection techniques (e.g., transmission
  lines), but not active component design.
• A major difference is that analog systems often
  have a bandwidth that is a small fraction of the
  carrier frequency whereas in digital systems
  generally require signal frequencies extending
  from DC to 2 or more times the highest clock
  frequency.
• The key issue is preservation of signal integrity.

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Outline and schedule

• Class Meeting Schedule
• August 27, 29
• September 3, 5, 10, 12, 17, 19, 24, 26
• October 1, 3, 8, 10, (no class on 15th), 17,
  22, 24, 29, 31
• November 5, 7, 12, 14, 19, 21, 26, (no class on
  28th)
• December 3, 5, 10, 12
• Final exam scheduled for Thursday, Dec 19, 130
  to 400 p.m.

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Course website

• URL people.eecs.ku.edu/callen/713/EECS713.htm
• Contains
• Syllabus
• Class assignments
• Some supplemental course material
• Project information (when issued)
• Powerpoint files used in class presentations
• continually updated to correct errors or enhanced
• file contents typically span many presentations
  (class sessions)
• max slide count 100
• Links to recorded presentations (audio and
  Powerpoint)
• Special announcements (when issued)

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Introductions

• Name
• Major
• Specialty
• What you hope to get from of this experience
• (Not asking what grade you are aiming for ?)

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What to expect

• Course is being webcast, therefore
• Most presentation material will be in PowerPoint
  format ?
• Presentations will be recorded and archived (for
  duration of semester)
• Not 100 reliable (occasionally recordings fail
  due to a variety of causes)
• Student interaction is encouraged
• Students must activate microphone before speaking
• Please disable microphone when finished
• Homework assignments will be posted on website
• Electronic homework submission logistics to be
  worked out
• We may have guest lecturers later in the semester
• To break the monotony, well take a couple of 1-
  to 2-minute breaks during each class session
  (roughly every 15 to 20 min)

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High-speed digital circuit design
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Your first assignment

• Send me an email (from the account you check most
  often)
• To callen_at_eecs.ku.edu
• Subject line Your name EECS 713
• Tell me a little about yourself and what
  knowledge you hope to gain from this experience
• Attach your ARTS form (or equivalent)
• ARTS Academic Requirements Tracking System
• Its basically an unofficial academic record
• I use this to get a sense of what academic
  experiences youve had

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Review

• Thevenin and Norton equivalent circuits
• Complex circuits can be modeled in terms of VT
  and ZT (Thevenin) or IN and ZN (Norton)Note that
  ZT ZN
• This concept applies to both analog and digital
  devicesboth inputs and outputs
• So we can determine the impedance (Z) of a
  source (driver) or a load

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Review

• Impedances are generally complex Z R jX
• R is real part (resistive)
• X is reactive part (inductive or capacitive)
• Of particular interest is the capacitive nature
  of the device as this often determines the
  circuits frequency response (time constant)
• Another important parameter is the drive devices
  current sourcing and sinking capacity (IN)
• These (sourcing / sinking) are not necessarily
  equal depending on the circuit design

20
Review

• Transmission lines
• Characteristic impedance, Zo V / I
• Velocity of propagation, vp lt c
• Propagation delay, d l / vp where l is the line
  length
• Impedance mismatches between the transmission
  line and the source impedance (ZS) or load
  impedance (ZL) it connects will reflect part of
  the impinging wave resulting in distortions in
  the voltage and current along the transmission
  line

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When are HSD design techniques needed?

• High-speed design (HSD) techniques (to be
  explored later) should be applied when the
  circuit trace length (the line length) l is
  greater than about a quarter of the length of the
  rising edge, l
• l gt l / 4
• Where
• and
• propagation delay (propagation velocity)-1

22
When are HSD design techniques needed?

• What is rise time ?
• Rise time or fall time (usually assumed to be
  equal) can be defined in a variety of methods
• Rise time, Tr, is defined as the time required
  for a signal to change from a specified low value
  to a specified high value.Typically these values
  are 10 and 90 of the step height.
• Others may use 20 and 80 of the step height
  or the step height divided by the center or
  maximum slope(See Appendix B in the text for
  more details)

23
When are HSD design techniques needed?

• Why use rise time, Trise, and not the clock
  frequency, fCLK?
• Consider the circuit
• In the time domain the output signal appears as

24
When are HSD design techniques needed?
In the frequency domain the output signal appears
as
The knee frequency, Fknee, which is inversely
related to the rise time, is much higher than
the clock frequency, FCLK.
Most energy in digital pulses concentrates below
the knee frequency. Any circuit with a flat
frequency response up to the Fknee frequency will
pass a digital signal practically undistorted.
25
When are HSD design techniques needed?

• What is propagation delay ?
• Signal delay is inversely related to signal
  velocity
• In free space, signals travel at speed of light,
  vp cc 3 x 108 m/s 30 cm/ns 11.8 in/ns
  0.0118 in/ps
• In free space, delay is Dfreespace 1/speed
  84.7 ps/in
• Propagation through a medium is slower than in
  free space.
• In non-free spacewhere ?r is the relative
  permeability and?r is the relative permittivity
  of the medium
• Typically, ?r 1 so thatwhere n refractive
  index

1 ns 10-9 s 1 ps 10-12 s 1 in 2.54 cm
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When are HSD design techniques needed?

• What is propagation delay ?
• Consider a stripline trace in FR-4 (?r 4.5, n
  2.12)
• Since the field lines are confined entirely
  within the glass-epoxy dielectric, the
  propagation velocity is simply

Trace A line or "wire" of conductive material
such as copper, silver or gold, on the surface of
or sandwiched inside a PCB, printed circuit
board.
Stripline transmission line geometry
FR-4 Flame-Retardant industrial laminate having
a substrate of woven-glass fabric and resin
binder of epoxy. FR-4 is the most common
dielectric material used in the construction of
PCBs in the USA
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When are HSD design techniques needed?

• What is propagation delay ?
• Now consider a microstrip trace on FR-4
• Here the field lines are not confined within the
  glass-epoxy dielectric, so the effective
  permittivity is between that of air (?r 1) and
  that of FR-4 (?r 4.5).
• Therefore the propagation velocity is between c
  and 0.47c.
• So for microstrip lines 85 ps/in (free space) lt
  D lt 180 ps/in (stripline).
• Furthermore, the propagation velocity may be
  frequency dependent leading to signal dispersion
  and pulse distortion.

Microstrip transmission line geometry
28
When are HSD design techniques needed?

• What is l ?
• l is the length of the rising edge and l Tr /D.
• Consider a circuit with Tr 800 ps (GaAs
  technology)
• Fknee for this signal will be (1600 ps)-1 or 625
  MHz
• The signal propagates on a stripline transmission
  line fabricated on alumina (?r 8.7).
• Find l
• So l/4 0.8 in or 2 cm
• Therefore if the circuit length l gt 2 cm HSD
  design techniques should be followed.

GaAs An alloy of gallium and arsenic compound
(GaAs) that is used as the base material for
chips.
Alumina A ceramic used for insulators in
substrates in thin film circuits. It can
withstand continuously high temperatures and has
a low dielectric loss over a wide frequency
range.  Aluminum oxide (Al2O3).
29
When are HSD design techniques needed?

• Failure to follow HSD design techniques may
  result in
• Signal reflections Cross talk Interference Ringing

30
Transient response of reactive circuits

• Reactances are not usually considered in
  low-speed digital circuit designs.
• Think about low-speed behavior as essentially DC
• Reactive circuit elements of interest
  includecapacitance load, distributed,
  parasiticinductance load, distributed,
  parasiticmutual capacitance capacitive
  couplingmutual inductance inductive coupling

31
Transient response of reactive circuits

• Whatever the nature of the reactance, we can
  treat it as a lumped quantity being driven by a
  signal generator.
• Consider the circuit loaded by a capacitor,
  driven by a step function.
• Predict the resulting output voltage (Vo(t)),
  current (I), and short-term impedance (i.e.,
  Vo(t)/I(t)) as the circuit responds to the
  stimulus.
• What will the output voltage be immediately after
  the step function?
• What will be the steady-state output voltage?
• What will the current be immediately after the
  step function?
• What will be the steady-state current?

32
Transient response of reactive circuits

• Time-domain viewpoint
• Capacitor voltage cannot change instantaneously
• Over short-time intervals capacitors behave as
  ideal voltage sources.
• For modeling purposes, capacitors are modeled as
  a short circuits.
• Long after the transient, the capacitor current
  goes to zero
• For modeling purposes, capacitors are modeled as
  open circuits.
• Inductor current cannot change instantaneously
• Over short-time intervals an inductor behaves as
  a current source.
• For modeling purposes, inductors are modeled as
  open circuits.
• Long after the transient, the inductor voltage
  goes to zero
• For modeling purposes, inductors are modeled as
  short circuits.
• Frequency-domain viewpoint
• At high frequencies, capacitors behave as shorts,
  inductors as opens
• At low frequencies, capacitors behave as opens,
  inductors as shorts

33
Transient response of reactive circuits

• Transient response to step function.

34
Transient response of reactive circuits

• Consider the circuit loaded by a perfect
  inductor, driven by a step function.
• Predict the resulting output voltage (Vo(t)),
  current (I), and short-term impedance (i.e.,
  Vo(t)/I(t)) as the circuit responds to the
  stimulus.
• What will the output voltage be immediately after
  the step function?
• What will be the steady-state output voltage?
• What will the current be immediately after the
  step function?
• What will be the steady-state current?

35
Transient response of reactive circuits

• Transient response to step function.

36
Transient response of reactive circuits

• Homework 1
• Following a similar procedure, predict the
  transient response for the four load conditions
  shown.

See the course website for homework assignment
details.
37
Measuring device reactance

• Sometimes is it necessary to measure reactance
  (capacitance inductance) of devices
• circuit structures (traces)
• packages
• leaded components
• Why not apply EM analysis instead ?
• too many unknowns (?r, internal geometry,
  material ?)
• complex geometries, difficult to measure or model
• cost in , time, resources
• Building a small test fixture may be
• more efficient and accurate
• relatively simple to fabricate

38
Measuring device reactance

• Test equipment requirements
• While specialized test equipment exists to
  characterize inductance, capacitance, resistance,
  etc., such instruments may not be available.
• More common instrumentation that may be used
  include
• Pulse generator with a small Tr value
• Oscilloscope with a wide bandwidth

see page 85 in text
Tr BW
100 ps 3.5 GHz
800 ps 440 MHz
2 ns 175 MHz
BW3dB bandwidth over which signal power falls
by 50 (3 dB)
39
Measuring device capacitance

• Capacitance test fixture design
• Simplified test circuit
• Thevenin equivalent circuit connected to unknown
  capacitive load, Z, also known as the Device
  Under Test (DUT)
• The output voltage from simple, first-order RC
  circuit is
• where ? is the circuits time constant, ? Rs C.
• If Rs is known, the unknown capacitance, C, can
  be estimated by observing the rise time ? of Vo

40
Measuring device capacitance

• If the anticipated DUT capacitance is a few pF,
  what value of Rs is required to provide a
  measurable ? ?
• Exampleassume pulse generators Tr 800 ps (BW
  0.35/800 ps 440 MHz)assume oscilloscopes BW
  ? 440 MHzoscilloscopes smallest useful time
  scale 500 ps / divtherefore we need ? ? 500 ps
• If we assume C 1 pF and set ? 500 ps, thenRs
  ? / C ? 500 ps / 1 pF orRs ? 500 ?

41
Measuring device capacitance

• Suggested capacitance test fixture design
• Determine values for R1 and R2 so that Rs ? 500 ?

42
Measuring device capacitance

• Capacitance test fixture design insights
• To reduce reflection which would corrupt the
  measurement the cables have Zo 50 ?the
  oscilloscope has internal termination of 50 ?the
  test fixture has termination of 50 ?the pulse
  generator has source termination of 50 ?
• Coaxial cables enter/exit from opposite sides to
  reduce direct feed-through
• R1 provides isolation between the source and the
  DUT
• R2 acts as a voltage divider with the
  oscilloscopes 50-? termination

43
Measuring device capacitance

• Suggested value for R2 is 1000 ? (1 k?)
• This keeps the scope from loading the capacitor,
  i.e., without R2, Rs 50 ?
• For R2 1000 ?, what should R1 be to make Rs ?
  500 ? ?To answer this, analyze the circuit as
  seen by the DUT

44
Measuring device capacitance

• The resistance between the DUT terminals written
  asRs (1000 50) // (R1 50 // 50) ? 500
  ? orRs (1050) // (25 R1) ? 500 ? or1/1050
  1/(25 R1) ? 1/500 orR1 ? 930 ?
• With 5 resistorschoices are910 ? or 1000 ?
• ThereforeR1 1000 ? andRs 519 ?

45
Measuring device capacitance

• We can test our setup by shorting the DUT test
  points
• ideal response should be zero
• Circuit analysis needed to
• predict the range of Vo
• select the power rating for resistors
• using steady-state analysis when V 1 V

46
Measuring device capacitance

• In steady state, treat DUT as open circuit
• Resistance seen by sourceR 50 50//2050 orR
  98.8 ?
• Source current, I1, isI1 1 V / 98.8 ?I1
  10.1 mA
• Node voltages and branch currents areVA 1
  (50) (I1) 494 mVI2 494 mV / 50 9.88 mAI3
  VA / 2050 241 ?AVB (1050) (I3) 253 mVVC
  12 mV
• Note that VB/VC 21a 211 voltage reduction

47
Measuring device capacitance

• Capacitance test fixture design
• Now find the power dissipation in various
  resistorsIn the pulse generators Rs, Pdiss
  RS(I1)2 5 mWIn the test fixtures 1-k?
  resistors, Pdiss 1k(I3)2 58 ?WIn the test
  fixtures 50-? resistor, Pdiss 50(I2)2 5 mW
• Therefore 1/8-W resistors can be used in the test
  fixture

48
Measuring device capacitance

• Capacitance test fixture application
• The Thevenin equivalent circuit for this test
  fixture is
• With the a component in the DUT, find the rise
  time ?when t ?, Vo Vs(1 e-1) 63.2 of
  Vs orVo 160 mV and Vmeas 7.58 mV
• ? corresponds to the point where ?V 7.58 mVC
  ? / 519 ?
• For example If ? 15 ns, then C 29 pF

Vmeas Vo / 21
49
Measuring device inductance

• Similar to the discussion on capacitance
  measurement, we can design a fixture for
  measuring device inductance.
• Setup designed to measure inductances as low as a
  few nH.
• Thevenin equivalent circuit connected to unknown
  inductive load, Z, also known as the Device Under
  Test (DUT).
• We know that the current through an inductor
  cannot change instantaneously, andwhere the
  time constant, ? L/Rs
• For L 1 nH (10-9 H) and a desired ? of 500
  psrequires Rs 2 ? (i.e., a small Rs value is
  desired)

50
Measuring device capacitance

• Suggested inductance test fixture design
• Determine values for R1 and R2 so that Rs lt 2 ?

51
Measuring device capacitance

• Design requirements
• R1 R2 50 ?
• at t 0 inductance behaves as open circuit
• Rs 50 // R2 // (R1 50)
• first 50 ? term represents oscilloscope
  termination
• second 50 ? term represents pulse generator
  termination

Notice There is no resistor between the DUT and
the oscilloscope? no voltage reduction, Vo
Vmeas Also notice Only R1 isolates the pulse
generator from the DUT? the 50- ? back
termination is very important to manage
reflections
52
Measuring device inductance

• Begin by letting R1 39 ? (from authors
  example)
• Therefore R2 10 ? ? Rs 7.6 ? does not meet
  2-? requirement
• Voltage applied across DUT will be Vs (10) / (50
  39 10) 10.1 of Vs

53
Measuring device inductance

• Try again, let R1 47 ?
• Therefore R2 2.2 ? ? Rs 2.06 ? meets 2-?
  requirement
• Voltage applied across DUT will be Vs (2.2) /
  (50 47 2.2) 2.2 of Vs

54
Measuring device inductance

• Now consider the effects of testing a component
  with both capacitance and inductance
• Example in text describes a DUT is a 1? long
  trace, 0.010? (10 mils) wide with a 0.035? (35
  mils) diameter via to ground.
• Estimated characteristics for this structure
  areC 2 pF, L 9 nH
• At the leading pulses leading edge (Tr 800 ps)
  the max frequency of interest is Fknee 0.5/Tr
  625 MHz
• The capacitive reactance, Xc (2 ? f C)-1 and
  for f Fknee Xc(fFknee) Tr/(? C) 800 ps
  /(? 2 pF) 127 O
• The inductice reactance, XL 2? f L and for f
  Fknee XL(fFknee) ? L / Tr ? 9 nH / 800 ps
  35 O

1?
Oblique view of ? microstrip trace and via....
10 mils
? Cross-section view of microstrip trace and via.
35 mils
55
Measuring device inductance

• Equivalent circuit for via using ? transmission
  line model
• Now, Xc 2Tr/(? C) 254 O
• The instantaneous impedance, Vo(t)/I(t) at t0,
  is
• XC // XL or 256 O // 35 O 30.8 O
• So the error in the measurement of XL is (35 -
  30.8) / 35 0.12? 12 error due to parasitic
  capacitance

?
56
Measuring device inductance

• Now find the inductance from the observed
  waveform
• at time t1,
• find time t2 on waveform so that
• ? t2 Rs/L 1 t1 Rs/L
• t2 t1 L/Rs ? L Rs (t2 t1)

57
Measuring device inductance

• The author also presents an alternative technique
  for finding L from the observed Vo(t) using the
  area under the curve.
• An advantage of this approach is that it is less
  sensitive to noise (measurement error) and less
  sensitive to the rise time.
• A disadvantage is that it requires integration of
  the waveform, however this may be achieved either
  using built-in math functions in modern
  oscilloscopes orby exporting the captured the
  waveform for external analysis.

58
Impact of via inductance

• Now consider the impact of via inductance on
  circuit performance. Consider the circuitA 50-?
  transmission line terminated with 50-? load
  resistor connected to ground through a via.
• Physically this may look like
• An equivalent circuit is

59
Impact of via inductance

• Instantaneous impedance at load end is
• (50 XL // XC) // 10k
• where XC Tr / (? C) and XL ? L / Tr
• For Tr 3 ns, XC 954 ? and XL 9.42 ?, XL //
  XC 9.3 ?
• The effective impedance to ground is 59
  ?resulting impedance mismatch produces a small
  reflection
• Reflection (ZL Zo) / (ZL Zo) 8

60
Impact of via inductance

• Now consider the impact of via inductance on a
  circuit where a bus of 8 lines use a single
  ground via for all 8 termination resistors.
• Physically this may look like
• An equivalent circuit is

61
Impact of via inductance

• Now the find the instantaneous impedance at load
  end for Tr 3 ns. We know that XL // XC 9.3
  ?
• Consider the case when all 8 lines transition low
  to high
• The effective transmission line impedance is
  6.25 ?and the effective impedance to ground is
  15.55 ?resulting a significant impedance
  mismatch
• Reflection (ZL Zo) / (ZL Zo) (15.55
  6.25) / (15.35 6.25) 43

62
Crosstalk from mutual reactance

• Consider the circuit
• In the absence of couplingthe signals A and B
  operateindependently, i.e., no crosstalk.
• Crosstalk between circuits can occur through
  mutual capacitance or through mutual inductance.

63
Crosstalk from mutual capacitance

• Mutual capacitance involved electric field
  interaction between circuits A and B.
• The magnitude of the mutual capacitance depends
  on the circuit geometry and on the material
  properties.
• We know IM CM dV/dt CM d(VA-VB)/dt
• Consider the case where VA VB
• static case both high or both low and
  unchanging
• dynamic case both transitioning low-to-high or
  high-to-low
• IM 0, no capacitive current flows

64
Crosstalk from mutual capacitance

• Now consider the case where VA ? VB
• signal A transitioning from low-to-high while
  signal B is static low
• Now dVA/dt ?V/Tr
• so IM CM ?V/Tr
• IM represents additional current flowing in
  circuit B

0
65
Crosstalk from mutual capacitance

• IM CM ?V/Tr flows into circuit B
• VB IM RB // RSB
• if RSB gtgt RB, then VB IM RB
• if RSB RB, then VB IM RB / 2
• This voltage can be thought of as crosstalk
• Unwanted signal IM RB // RSB CM (RB // RSB)
  ?V/Tr
• Pure signal in B is ?V

66
Crosstalk from mutual capacitance

• The resulting crosstalkfor capacitive
  couplingappears as
• Can we measure CM ?For a known ?V, Tr, RB ltlt RSB
  
• Integrate both sides to get
• so

67
Crosstalk from mutual inductance

• Interaction between circuits can also result
  through magnetic field coupling, this is called
  mutual inductance.
• The magnitude of mutual inductance depends on
  the geometry of the circuit.
• Recall,
• assume
• If reactance of inductance ltlt RA and RA ltlt RSA
• then

68
Crosstalk from mutual inductance

• So we have
• Recalling our definition of crosstalk
• we have
• The resulting crosstalkfor inductive
  couplingmay appear as
• The circuit geometry will determine polarity of
  inductive crosstalk, so polarity of signal
  induced into circuit B could be negative.

69
Crosstalk from mutual inductance

• Can we measure LM ?For a given ?V, Tr, RA ltlt RSA
  we know
• Integrate both sides to get

so
70
Crosstalk from mutual inductance

• Actually the induced voltage pulse is split
  across the inductor.
• So half of Vx is seen at RB initially and the
  area under the curve must be doubled to
  correctly estimate LM.
• So

71
Crosstalk from mutual reactance

• Note that the sign of Vx can be positive or
  negative depending on the dot convention which
  depends on the circuit geometry.
• Mutual inductancemay produce this ?
• in circuit B
• or this ?
• Whereas capacitively
• generated signals in B

72
Crosstalk from mutual reactance

• How to reduce crosstalk?
• Recall that the source is coupled fields
• electric fields ? capacitance
• magnetic fields ? inductance
• techniques to reduce field coupling ? reduced
  crosstalk
• Examples include
• increasing separation between circuits
• reduce the loop area for inductive coupling
• reduce the area for capacitive coupling
• Other approaches
• introduce isolating structures (guard traces or
  fence of ground vias)
• increase Tr if possible