ICSemiconductor Design and Manufacturing Overview - PowerPoint PPT Presentation

Title: ICSemiconductor Design and Manufacturing Overview


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IC-Semiconductor Design and Manufacturing
Overview

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Typical Integrated Circuit (IC) Design Flow
(Hewlett Packard)
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Integrated Circuit Simulation
Thirty years ago, the tools that made the
engineering knowledge practical included the
drawing board and the slide rule. Nowadays, the
tool chest includes computers and engineering
software -Out of a great variety of different
computer programs, the electronic circuit
simulator SPICE (on which MultiSim is based) is
probably the most important for electrical
engineers. -The SPICE program, originated and
developed at University of California at
Berkeley, is truly a wonderful present to the
electrical engineering community worldwide from
one of the best American public universities. It
allows us to simulate both individual devices and
electronic circuits, performing a large number of
different analyses needed for tasks such as
verification of circuit designs and prediction of
circuit performance. It is so flexible and
usually so reliable that many engineers use it as
a "software oscilloscope". However, the results
of a SPICE simulation are only as good as the
device models and the device parameters used in
the simulation. Device technologies change so
fast and device characteristics are so different
that just using default parameters is almost
never justified. If wrong device parameters or
models are used in a SPICE simulation, all this
computer power will be wastedtrue to the old
adage "Garbage in, garbage out". Less than a
decade ago, a typical circuit simulator would run
only on mainframe computers. However, the rapid
progress in microcomputers has enabled the
development of SPICE versions that can run on
inexpensive machines, making advanced circuit
simulators readily available practically to every
electrical engineer and electrical engineering
student. Hence, we are now in the privileged
situation that we can teach a course on the
basics of semiconductor device physics and device
modeling using the same computer aided design
(CAD) tool that electrical engineering students
will almost certainly use as practicing
engineers. This fortunate circumstance allows
students to try actual circuit design, bringing
semiconductor device physics and modeling (which
are often taught as a fairly theoretical subject)
down to a very practical level.
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Semiconductor Manufacturing Processes

• Design
• Wafer Preparation
• Front-end Processes
• Photolithography
• Etch
• Cleaning
• Thin Films
• Ion Implantation
• Planarization
• Test and Assembly

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Design

• Establish Design Rules
• Circuit Element Design
• Interconnect Routing
• Device Simulation
• Pattern Preparation

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Pattern Preparation
Reticle
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Wafer Preparation

• Polysilicon Refining
• Crystal Pulling
• Wafer Slicing Polishing
• Epitaxial Silicon Deposition

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Polysilicon Refining
Chemical Reactions Silicon Refining SiO2
2 C ? Si 2 CO Silicon Purification Si 3
HCl ? HSiCl3 H2 Silicon Deposition HSiCl3
H2 ? Si 3 HCl
Reactants H2 Silicon Intermediates
H2SiCl2 HSiCl3
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Crystal Pulling
Process Conditions Flow Rate 20 to 50
liters/min Time 18 to 24 hours
Temperature gt1,300 degrees C Pressure 20
Torr
Materials Polysilicon Nodules Ar
H2
High proportion of the total product use
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Wafer Slicing Polishing
The silicon ingot is sliced into individual
wafers, polished, and cleaned.
3/15/98
PRAX01C.PPT Rev. 1.0
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Epitaxial Silicon Deposition
Gas Input
Lamp Module
Susceptor
Chemical Reactions Silicon Deposition
HSiCl3 H2 ? Si 3 HCl Process Conditions
Flow Rates 5 to 50 liters/min Temperature
900 to 1,100 degrees C. Pressure 100 Torr
to Atmospheric
Quartz Lamps
Wafers
Exhaust
High proportion of the total product use
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Front-End Processes

• Thermal Oxidation
• Silicon Nitride Deposition
• Low Pressure Chemical Vapor Deposition (LPCVD)
• Polysilicon Deposition
• Low Pressure Chemical Vapor Deposition (LPCVD)
• Annealing

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Front-End Processes
Chemical Reactions Thermal Oxidation Si O2
? SiO2 Nitride Deposition 3 SiH4 4 NH3 ?
Si3N4 12 H2 Polysilicon Deposition SiH4 ?
Si 2 H2 Process Conditions (Silicon Nitride
LPCVD) Flow Rates 10 - 300 sccm
Temperature 600 degrees C. Pressure 100
mTorr
Polysilicon H2 N2 SiH4 AsH3
B2H6 PH3
Nitride NH3 H2SiCl2 N2 SiH4
SiCl4
Oxidation Ar N2 H2O Cl2 H2
HCl O2 Dichloroethene
Annealing Ar He H2 N2
High proportion of the total product use
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Photolithography

• Photoresist Coating Processes
• Exposure Processes

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Photoresist Coating Processes
photoresist
field oxide
p- epi
p substrate
Photoresists Negative Photoresist
Positive Photoresist Other Ancillary Materials
(Liquids) Edge Bead Removers
Anti-Reflective Coatings Adhesion
Promoters/Primers (HMDS) Rinsers/Thinners/Co
rrosion Inhibitors Contrast Enhancement
Materials Developers TMAH Specialty
Developers Inert Gases Ar N2
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Exposure Processes
Expose Kr F2 (gas) Inert Gases N2
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Ion Implantation

• Well Implants
• Channel Implants
• Source/Drain Implants

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Ion Implantation
junction depth
Process Conditions Flow Rate 5 sccm
Pressure 10-5 Torr Accelerating Voltage 5
to 200 keV
High proportion of the total product use
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Etch

• Conductor Etch
• Poly Etch and Silicon Trench Etch
• Metal Etch
• Dielectric Etch

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Conductor Etch
Chemical Reactions Silicon Etch Si 4 HBr
? SiBr4 2 H2 Aluminum Etch Al 2 Cl2 ?
AlCl4 Process Conditions Flow Rates 100 to
300 sccm Pressure 10 to 500 mTorr RF
Power 50 to 100 Watts
High proportion of the total product use
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Dielectric Etch
Chemical Reactions Oxide Etch SiO2 C2F6 ?
SiF4 CO2 CF4 2 CO Process Conditions
Flow Rates 10 to 300 sccm Pressure 5 to
10 mTorr RF Power 100 to 200 Watts
High proportion of the total product use
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Cleaning

• Critical Cleaning
• Photoresist Strips
• Pre-Deposition Cleans

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Critical Cleaning
Process Conditions Temperature Piranha
Strip is 180 degrees C.
RCA Clean SC1 Clean (H2O NH4OH H2O2)
SC2 Clean (H2O HCl H2O2) Piranha Strip
H2SO4 H2O2
Nitride Strip H3PO4 Oxide Strip HF
H2O
Solvent Cleans NMP Proprietary Amines
(liquid) Dry Cleans HF O2 Plasma
Alcohol O3
Dry Strip N2O O2 CF4 O2 O3
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Thin Films

• Chemical Vapor Deposition (CVD) Dielectric
• CVD Tungsten
• Physical Vapor Deposition (PVD)
• Chamber Cleaning

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Chemical Vapor Deposition (CVD) Dielectric
TEOS Source
Chemical Reactions Si(OC2H5)4 9 O3 ? SiO2
5 CO 3 CO2 10 H2O Process Conditions (ILD)
Flow Rate 100 to 300 sccm Pressure 50
Torr to Atmospheric
High proportion of the total product use
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Chemical Vapor Deposition (CVD) Tungsten
Input Cassette
Output Cassette
Chemical Reactions WF6 3 H2 ? W 6
HF Process Conditions Flow Rate 100 to 300
sccm Pressure 100 mTorr Temperature
400 degrees C.
Wafer Hander
Wafers
Multistation Sequential Deposition Chamber
CVD Dielectric WF6 Ar H2 N2
Water-cooled Showerheads
Resistively Heated Pedestal
High proportion of the total product use
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Physical Vapor Deposition (PVD)
Physical Vapor Deposition Chambers
Cluster Tool Configuration
Wafers
Transfer Chamber
Loadlock
Process Conditions Pressure lt 5 mTorr
Temperature 200 degrees C. RF Power
Reactive Gases
PVD Chamber
Cryo Pump
Barrier Metals SiH4 Ar N2 N2
Ti PVD Targets
Transfer Chamber
e -

Wafer
Backside He Cooling
Argon Nitrogen
DC Power Supply ()
High proportion of the total product use
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Chamber Cleaning
Chemical Reactions Oxide Etch SiO2 C2F6 ?
SiF4 CO2 CF4 2 CO Process Conditions
Flow Rates 10 to 300 sccm Pressure 10 to
100 mTorr RF Power 100 to 200 Watts
Chamber Cleaning C2F6 NF3 ClF3
Chamber Wall Cross-Section
High proportion of the total product use
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Planarization

• Oxide Planarization
• Metal Planarization

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Chemical Mechanical Planarization (CMP)
Process Conditions (Oxide) Flow 250 to 1000
ml/min Particle Size 100 to 250 nm
Concentration 10 to 15, 10.5 to 11.3 pH Process
Conditions (Metal) Flow 50 to 100 ml/min
Particle Size 180 to 280 nm Concentration
3 to 7, 4.1 - 4.4 pH
Wafer Carrier
Polishing Pad
Slurry Delivery

Wafer
Platen
High proportion of the total product use.
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Test and Assembly

• Electrical Test Probe
• Die Cut and Assembly
• Die Attach and Wire Bonding
• Final Test

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Electrical Test Probe
Defective IC
Individual integrated circuits are tested to
distinguish good die from bad ones.
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Die Cut and Assembly
Good chips are attached to a lead frame package.
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Die Attach and Wire Bonding
lead frame
gold wire
bonding pad
connecting pin
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Final Test
Chips are electrically tested under varying
environmental conditions.