332:437 Lecture 4 VariableEntered Karnaugh Maps and MixedLogic Notation - PowerPoint PPT Presentation

Title: 332:437 Lecture 4 VariableEntered Karnaugh Maps and MixedLogic Notation


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332437 Lecture 4Variable-Entered Karnaugh Maps
and Mixed-Logic Notation

• Variable-Entered Karnaugh Maps
• MUX-based and Indirect-Addressed MUX Design
• ROM-based Logic design
• Buffers and drivers
• Mixed-Logic notation
• Summary

Material from An Engineering Approach to Digital
Design, by W. I. Fletcher, Prentice-Hall
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Variable-Entered Karnaugh Maps (VEM)

• Allow 8 to 16 variable maps to be represented as
  3 to 5 variable maps
• Needed because typical Boolean design problem
  involves 8 or more Boolean variables

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Six-Variable K-Map
AB CD 00 01 11 10
EF 01
EF 00
EF 10
EF 11
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Variable-Entered Map (VEM)

• Conventional logic minimization
• Time consuming
• Error-prone
• VEM Key idea
• Represent values of function in terms of its
  variables (called map-entered variables) within
  Karnaugh map framework
• Group like variables in Karnaugh map cells

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Example VEM

• f (a, b, c) a b c a b c a b c a b c
• Arbitrarily choose c as map entered variable

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XOR/XNOR Gate Grouping

• New way of grouping map variables
• For this example
• f c b

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Example Result

• VEM technique reduced an ordinary 3-variable
  K-map to a 2-variable map
• Must group only like minterms in VEM
• f c ( b ) c (a b)

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Conventional K-Map Method

• f (c b) a a b
• Conventional Way
  VEM Way
• 2-input gates 4
  4
• inverters 2
  0

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Use of DeMorgans Theorems to Transform Logic
Gates
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VEM Techniques

• Use as many map-entered variables as you like
• Works well for partially-minimized functions
  use remaining variables as map-entered variables.
• Example
• f (w, x, y, z) Sm (3, 4, 6, 7, 10) Sd (9, 11,
  12, 14, 15)
• Choose w, x, y as ordinary K-map variables
• Make z the map-entered variable
• Only appears inside K-map entries

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Example (continued)
Map Entry 0 z z 1 z z z X z X z X z
X
w 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
z 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
f 0 0 0 1 1 0 1 1 0 X 1 X X 0 X X

• Truth table

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Example (concluded)

• Variable-Entered K-Map
• f y z x z w y z

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MUX-Based Logic Design

• Use circuit inputs to select from a variety of
  Boolean functions for the circuit output
• Functions wired to MUX inputs
• Often more efficient than SOP or POS design
• Problem Sometimes you need a 5-input MUX (32
  different input function selections), but there
  are really only 5 distinctly different input
  functions
• Wastes chip area with a large MUX
• Solution Indirect-addressed MUX

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Example Indirect-Addressed MUX-Based Design

• Example truth table Substitute ROM for MUX

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ROM and MUX Implementation
ROM 000 001 001 010 010 011 011 100 100 001 101
110 000 A0 A1 A2
Word Address a b c d e
00001 to 01111 (odd only) 00000 01000 00010 01010
00100 01100 00110 01110 10000 to 10011 10100
to 10111 11000 to 11111 All others
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Straight ROM Logic Implementation

• Sometimes the best design method

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Alternate Discrete Logic Implementation

• May very well use as much chip area as ROM
  implementation each ROM cell needs only 1
  transistor

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Logic Gate Choices

• Extra unused inputs
• Terminate properly by connecting to
  non-controlling logic value
• OR/NOR/XOR connect to 0 (Vss)
• AND/NAND connect to 1 (VDD through pullup
  resistor)
• EQUIVALENCE connect to 1
• Unconnected extra inputs act like radio antennas
• Collect electrical noise randomly fluctuate
  between logic 0 1

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Choice of Logic Realization

• CMOS, nMOS, TTL logic families
• Fewer transistors in NAND/NOR gates than in
  AND/OR gates
• NAND/NOR also faster than AND/OR
• Gate substitution Use 3-input AND gate instead
  of cascaded 2-input ANDs (faster)

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Form Substitution

• All 3 realizations are exactly the same, but the
  single NOR gate realization is better

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Buffers/Drivers

• Buffers have more driving current than ordinary
  CMOS gates used for large fanout gates (more
  than 8-10).
• Do not load up an ordinary CMOS gate with more
  than 8-10 gates

Delay t1 n t2
Delay t1 t2
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Buffers/Drivers (continued)

• Drivers adapted for higher current voltage
  levels than buffers
• Examples TTL CMOS, CMOS TTL
  conversions
• Reason TTL output I-V specification does not
  match analog circuit specification
• Examples relays, analog switches, fluorescent
  displays, appliance controls
• High-Voltage Drivers
• Usually have open-collector
  Bipolar outputs

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Buffers/Drivers (continued)

• Line drivers provide (source) large I or accept
  (sink) large I
• Source 40 mA with 50W load
• Sink 60 mA
• For interface lines (long) between digital
  systems
• Bus driver Line Driver with tri-state output
• When disabled, goes into high impedance state
  at output

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Buffers/Drivers (continued)

• Line Receiver actually a driver used at
  receiving end of bus interface to latch amplify
  signals sent over bus
• Load on bus is single load but signal amplified
  sent many places

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Logic Types

• Positive Logic (active high)
• 0 0 V., 1 1.0 V.
• Negative Logic (active low)
• 0 1.0 V., 1 0 V.
• Mixed-Logic logic with
• Negative (positive) logic inputs
• Positive (negative) logic outputs
• Arbitrary mixture of positive negative logic
• Most systems designed this way
• Can be confusing

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Mixed Logic Notation

• Load Active high signal
• /Load Active low signal
• /Load Load
• Load /Load

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Multiple Gate Interpretations

• Positive logic Negative logic

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Why Do We Need Negative Logic?

• Easier to hold unused inputs of circuit at high
  voltage level rather than at low voltage level
• Hold many unused inputs high only active ones
  need to be held low
• Easier to label signals in terms of their
  functions whether or not data is positive or
  negative
• Example IN / OUT
• Often get better noise immunity with negative
  logic than with positive logic
• Particularly true on buses
• Low hardware noise margin often better than high
  hardware noise margin

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Mixed-Logic Design Rules

• If an input (output) is negative, LABEL IT with /
  and make sure that it flows into (from) a bubble
• If an input (output) is positive, DO NOT LABEL IT
  with / and make sure that it does not flow into
  (from a bubble)
• Not always possible to follow these rules in
  every part of the circuit due to Boolean function

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Example

• If A, B, C are negative logic, better notation
• Meaning If A is turned on or B is turned on,
  then C is turned on
• Negative logic has the OR operation, so the
  negative logic picture corresponds to that

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Real-Life Circuit Design

• Mixed-logic occurs most frequently
• 2-level SOP or POS forms may use way too much
  hardware
• Always true for very large circuits
• Instead, use multi-level logic

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Transformations

• Can always add bubbles to both ends of a wire
  without changing circuit function
• Turn AND-OR into NAND-NAND form

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Summary

• Variable-Entered Karnaugh Maps
• MUX-based and Indirect-Addressed MUX Design
• ROM-based Logic design
• Buffers and drivers
• Mixed-Logic notation