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On Designing ViaConfigurable Cell Blocks for Regular Fabric
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... of Electrical and Computer Engineering. University of California, Santa ... Patel et al. 'An architectural exploration of via patterned gate arrays', ISPD'03 ... – PowerPoint PPT presentation
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Title: On Designing ViaConfigurable Cell Blocks for Regular Fabric
1
On Designing Via-Configurable Cell Blocks for
Regular Fabric
- Yajun Ran
- Malgorzata Marek-Sadowska
- Department of Electrical and Computer Engineering
- University of California, Santa Barbara
2
Standard-Cell and FPGAs
- High performance, small area, low power
consumption - Huge development and mask cost, long turn-around
time - Design rule, manufacturability
- Easy to design and debug, fast time-to-market
- Low performance, large area, high power
consumption - High unit cost
3
Structured ASICs - Filling in the gap
- Give up field programmability
- Mask programmable
- Discard active switches
- Many parts pre-fabricated
- Pre-fabricated transistors
- Fixed lower-level interconnect
- Via-programmable fabric
- Customized via masks
4
Via-Patterned Gate Array (VPGA)
- Patel et al. An architectural exploration of via
patterned gate arrays, ISPD03
5
Hybrid Cell Block
D
CK
- Pileggi et al. Exploring Regular Fabrics to
Optimize the Performance Cost Trade-Off, DAC03
6
Our Via-Configurable Cell (VCC)
Vdd
P-diff
N-diff
Poly
M1
M2
Contact
Gnd
7
Cell function and layout
8
VCC-realizable function enumeration
M
M
9
Functional coverage of n-VCC
- Z. A. Lomnicki, Two-Terminal Series-Parallel
Networks, Advances in Applied Probability, 1972
10
Intra-cell wire requirement
8-VCC N(P)-part
- M2 rows required is 2(?(n-1)/2?2)
11
Wire segmentation
8-VCC N-part
x1 x2 x3 x4 x5 x6 x7 x8
Example f (x1x2x3)(x4x5x6(x7x8))
12
Wire segmentation
8-VCC N-part
x1 x2 x3 x4 x5 x6 x7 x8
Example f (x1x2x3)(x4x5x6(x7x8))
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Multiple-Gate Implementation
vdd
gnd
14
Via-Decomposable DFF
15
Via-Configurable MUX21
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Via-Configured Sizable Repeater Array
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Via-Configured Sizable Repeater Array
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Experimental setting
- Single block type
- 20 Largest MCNC benchmarks (2k 14k)
- FF 0 1.5k
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Evaluation flow
- Synthesis and mapping
- Greedy packing
- Block-level placement (Capo)
- Standard-cell-like global routing
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Experimental Results - Area
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Experimental Results - Delay
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Experimental Results Power consumption
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Experimental Results - Transistor utilization
24
Conclusions Future work
- Via-configurable cell
- Compact layout
- Strong functional expression
- Fast and less power-consuming
- Via-decomposable FF
- Can be configured into combinational gates
- Improves cell utilization
- Future work
- Fixed routing structure
- Fabric-specific design flow
25
Thank you!
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