James Joyner, Payman ZarkeshHa, - PowerPoint PPT Presentation

Title: James Joyner, Payman ZarkeshHa,


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A Global Interconnect Design Window for a
Three-Dimensional System-on-a-Chip

• James Joyner, Payman Zarkesh-Ha,
• and James Meindl
• Microelectronics Research Center
• Georgia Institute of Technology
• IITC 2001
• 5 June 2001
• Supported by DARPA and SRC

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Outline

• Motivation
• Global Design Plane for 2D-SoC
• Global Design Plane for 3D-SoC
• Conclusions

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The Interconnect Problem
10 of Interconnects 80 of Wire Length KEEP
INTERCONNECTS SHORT!!
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The 3D Proposal
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3D Homogeneous Distribution
4 million gates, k4, p0.6
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Interconnect Length in 3D
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Interstratal Interconnect Density Limitations
Cross-section
Pad - Stratum 1
Alignment Tolerance
Pitch
Pad - Stratum 2
Demonstrated alignment tolerance for wafer
bonding of 1 micron requires bonding pads of at
least 5 microns. Heterogeneous 3D-SoC may
require less interstratal interconnect density
since only global nets would be routed vertically.
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Outline

• Motivation
• Global Design Plane for 2D-SoC
• Global Design Plane for 3D-SoC
• Conclusions

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Global Interconnects in an SoC
Global net-length distribution
In an SoC, global nets are those connecting
multiple megacells.
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Designing Global Interconnects

• Global design plane is used to determine
  interconnect width and height for the global
  tier.

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Clock Frequency Constraint

• Goal meet a global clock frequency by increasing
  cross-sectional area.

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Wiring Area Constraint
Goal equate wiring area needed to available
wiring area to meet IR drop constraint by
limiting width and increasing height.
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Crosstalk Noise Constraint
Goal meet a target percentage crosstalk noise on
signal lines by limiting mutual capacitance.
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Global Interconnect Design Window
Bandwidth
Noise
Max Clock Frequency
Demand
Min Pitch
Min Aspect Ratio
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Design Window Scaling
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Outline

• Motivation
• Global Design Plane for 2D-SoC
• Global Design Plane for 3D-SoC
• Conclusions

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Layout of 3D-SoC
Total silicon area is conserved as megacells are
placed in 3D.
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3D Global Net Distributions
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180 nm Design Window
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50 nm Design Window
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I/O Density
I/O density must increase as the number of strata
increases.
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Maximum Global Clock Frequency
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Maximum Global Clock Frequency

• Solve all three constraints simultaneously
• Required I/O density
• Trading off-chip I/O for on-chip bandwidth!!

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Outline

• Motivation
• Global Design Plane for 2D-SoC
• Global Design Plane for 3D-SoC
• Conclusions

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Conclusions

• Global net length reduces as the square root of
  the number of strata.
• Interstratal interconnect density is not as
  demanding in heterogeneous as homogeneous.
• Global interconnect design window is greatly
  expanded by using a 3D-SoC.
• Off-chip I/O density can be traded for on-chip
  bandwidth (2.8x increase in bandwidth for 2x
  increase in I/O density).
• High I/O density packaging solutions can
  alleviate growing constraints of interconnects.