Soft Error Rates with Inertial and Logical Masking

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Soft Error Rates with Inertial and Logical
Masking Fan Wang Vishwani D. Agrawal vagrawal_at_en
g.auburn.edu
Department of Electrical and Computer
Engineering Auburn University, AL 36849 USA
22 th IEEE International Conference on VLSI Design
Presently with Juniper Networks, Inc. Sunnyvale,
CA
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Outline

• Background
• Problem Statement
• Analysis
• Results and Discussion
• Conclusion

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Motivation for This Work

• With the continuous downscaling of CMOS
  technologies, the device reliability has become a
  major bottleneck.
• The sensitivity of electronic systems can
  potentially become a major cause of soft
  (non-permanent) failures.
• The determination of soft error rate in logic
  circuits is a complex problem. It is necessary to
  analyze circuit reliability. However, there is no
  comprehensive work that considers all the factors
  that influence the soft error rate.

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Strike Changes State of a Single Bit
0
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Definition from NASA Thesaurus Single Event
Upset (SEU) Radiation-induced errors in
microelectronic circuits caused when charged
particles also, high energy particles (usually
from the radiation belts or from cosmic rays)
lose energy by ionizing the medium through which
they pass, leaving behind a wake of electron-hole
pairs.
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Cosmic Rays
Source Ziegler et al.

• Neutron flux is dependent on altitude,
  longitude, solar activity etc.

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Problem Statement

• Given background environment data
• Neutron flux
• Background energy (LET) distribution
• These two factors are location dependent.
• Given circuit characteristics
• Technology
• Circuit netlist
• Circuit node sensitive region data
• These three factors depend on the circuit.
• Estimate neutron caused soft error rate in
  standard FIT units.
• Linear Energy Transfer (LET) is a measure of the
  energy transferred to the device per unit length
  as an ionizing particle travels through material.
  Unit MeV-cm2/mg.
• Failures In Time (FIT) Number of failures per
  109 device hours

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Measured Environmental Data

• Typical ground-level neutron flux 56.5cm-2s-1.
• J. F. Ziegler, Terrestrial cosmic rays, IBM
  Journal of Research and Development, vol. 40, no.
  1, pp. 19.39, 1996.
• Particle energy distribution at ground-level
• For both 0.5µm and 0.35µm CMOS technology
  at ground level, the largest population has an
  LET of 20 MeV-cm2/mg or less. Particles with
  energy greater than 30 MeV-cm2/mg are exceedingly
  rare.
• K. J. Hass and J. W. Ambles, Single Event
  Transients in Deep Submicron CMOS, Proc. 42nd
  Midwest Symposium on Circuits and Systems, vol.
  1, 1999.

Probability density
0 15 30
Linear energy transfer (LET), MeV-cm2/mg
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Proposed Soft Error Model
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Pulse Width Probability Density Propagation
fX(x)
Delay tp
fY(y)

• We use a 3-interval piecewise linear
  propagation model
• Non-propagation, if X tp.
• Propagation with attenuation, if tp lt X lt 2tp.
• Propagation with no attenuation, if X ? 2tp.
• Where
• X input pulse width
• Y output pulse width
• tp gate input to output delay

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Probability Transformation

• Consider random variables x and y, and
• Function, Y F(X)
• Given, P.D.F. of X is p(x)
• P.D.F. of Y p(x)dx p(y)dy p(y) p(x)/(dy/dx)
  

ydy y
Y F(X)
X
x xdx
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Validation Using HSPICE Simulation

• CMOS inverter in TSMC035 technology with load
  capacitance 10fF

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Comparing Methods
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Experimental Results Comparison
BPTM Berkeley Predictive Technology Model
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More Result Comparison
The altitude is not mentioned for these data.
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Circuit Topology and SER

• Circuit topology influences the logic SER.
• We have analyzed two types of circuits for
  different sizes, an inverter chain and a ripple
  carry adder.
• For inverter chain, in TSMC035 technology the
  critical width is between 25ps and 50ps.
• For ripple carry adder, the critical width may
  not exist.

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Inverter Chain and SER
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Ripple Carry Adder and SER
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Conclusion

• SER in logic and memory chips will continue to
  increase as devices become more sensitive to soft
  errors at sea level.
• By modeling the soft errors by two parameters,
  the occurrence rate and single event transient
  pulse width density, we effectively account for
  the electrical masking of circuit.
• Our research on critical width of SER for
  different circuit topologies may provide better
  insights for soft error protection schemes.

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References

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  Sylvester, An Efficient Static Algorithm for
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• 3 G. Asadi and M. B. Tahoori, An Accurate
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Thank You . . .