Experience of Saclay on fast analog samplers

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• Experience of Saclay on fast analog samplers
• E. Delagnes1
• 1 CEA/DAPNIA SACLAY.
• EMAIL eric.delagnes_at_cea.fr.

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Motivations

• Need to digitize the signal closer and closer
  from the detector
• Digital signal is easier to transport.
• Power of digital treatment filter, PSD
• Digital data are easy to store.
• ..
• But limited by
• ADCs performances (continuous progress).
• 1994 800 mW x 10 bits x 40 Méchantillon/s
• 2004 800mW x 12bits x 200 Méchantillon/s
• Difficulty to treat the high continuous digital
  rate at the ADC output.
• Solution use analog memory before A/D
  conversion gain in performances
  (dynamiquesampling frequency/power) of more one
  order of magnitude possible

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Analog memories principle

• High frequency sampling on a track hold bank
  realised with a Switched Capacitor Array (capa
  MOS switches).
• Memorisation.
• Reading back of the data (selective or total,
  multiplexing) .
• Write and read operation can be simultaneous or
  not
• Analog heart with a digital control environment.

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Possible uses in physics experiments.

• ANALOG TRANSIENT RECORDER time expender.
• Analog delay line (need a readout as fast as the
  write operation).
• Level 1 buffer or filter in HEP experiments.

CK40 MHz
Préampli. filter
Write
DAQ
Analog Pipeline
ADC
Selective readout of a given Number of cells
Lv 1 trigge (1.5µs latency)
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The Analog Sampler history in SACLAY
SCTA32 95 Tracker ATLAS 32 ch/ 128 pts Fe 40
Mhz BP 10 Mhz Dyn 8 bits DMILL 0.8 µm
ARS0 97-98 ANTARES/HESS1 5 ch/ 128 pts Linear
Structure Fe 1Gs/S BP 80 Mhz Dyn8-9bits AMS
0.8 µm
ARS1 98-04 ANTARES 4 ch System on chip Using
the ARS0
HAMAC 93-97 Calo ATLAS 12 ch/ 144 pts Fe 40
Mhz BP 10 Mhz Dyn 13,6 bits DMILL 0.8 µm
SAM 04-05 HESS2 2 channels / 256 pts Fe
700MHz-2GHz BP 300 Mhz Dyn 12 bits AMS 0.35 µm
MATACQ 99-01 METRIXgt DEMIN Matrix structure 1
canal, 2560 pts Fe 50 MHz-2GHz BP 300 Mhz Dyn
12 bits AMS 0.8 µm
PIPELINE 01- 02 METRIX 1 canal System on chip
based on MATACQ
Collaboration with IN2P3/LAL
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The beginning of the history
- L1 Buffer of ATLAS LARG calorimeter -
Simultaneous Write/read  dead-time free . -12
channels of 144 cells - Analog multiplexing
toward a 5MHz ADC - RADHARD (technologie DMILL,
CMOS 0.8). - Fsample 40 MHz, BW 50 MHz. -
Dynamique range (300µV/4V) gt 13 bits (world
record). - 80000 chips manufactured, tested and
delivered.
-Start of RD (RD3 in 94). -Final design in
97. -Production of 80000 chips in
2001-2002. -Tests in 2002-2003. -Delivery in
2004.
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The ARS0 chip initially designed for ANTARES

• Gsample/s time expander chip originally developed
  for the ANTARES experiment.
• Based on sampling-DLL technique
• 5 channels /chip, 128 cells per channel.
• Sampling _at_ 1 GHz
• Readout 1 MHz/sample triggered by an external
  signal
• A programmable number of cells is read
• starting from a programmable offset from the
  trigger
• Low power (500mW).
• 8-9 bits dynamic range

AMS CMOS 0.8µm
Heart of the ARS1 chip for ANTARES Used _at_ CEBAF
by IN2P3/LPC Used by HESS I
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The ARS0 chip in HESS I
Camera digitizing electronics
The HESS high energy gamma observatory in NAMIBIA
FPGA
DAQ
Two read-out modes are available sample all
the cells of the selected window are read.
charge The cells of the window are summed
inside the FPGA
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The MATACQ chip.

• A time expander based on a new MATRIX1 structure
  for extended performances higher bandwidth,
  longer memory depth (2560 cells), programmable
  sampling frequency.
• Also includes an analog TVC for ps range timing.
• Heart of the MATACQ board (VME GPIB)
  industrialized by CAEN1.

AMS 0.8µm CMOS.1channel/chip
4 channels version (exist also with 8 channels
_different form factor)
1 Very High Dynamic Range and High Sampling
Rate VME Digitizing Boards for Physics
Experiments, D. Breton, E. Delagnes, Proceedings
of NSS 2004 ROMA, should be published in IEEE TNS
2005,12. Preprints available on request
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MATACQ some applications.

• Some Applications
• neutron TOF measurements on a 160 channel
  Micromegas detectors (DEMIN).
• Digitization in CAST experiment
• Test of PMT _at_ IN2P3/IPNO
• Serie-Test of the ATLAS LARG Board.
• Timing on Chimera

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PIPELINE The Heart of a hand-held oscilloscope

• PIPELINE is a system on chip including a similar
  SCA designed by us.
• Includes 250000 transistors.
• Heart of a hand held oscilloscope developed by
  CHAUVIN-ARNOUX METRIX
• Its Front-end uses very few other components than
  PIPELINE.

1GS/S 100MHz BW Up to 4 floating input
channels with 600V insulation
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The Swift Analog Memory chip for HESS2.

• A new biggest telescop is being constructed to
  decrease the energy treshold of the experiment to
  10 GeV gt HESS2
• Increase drastically the rate and the dynamic
  range.
• Use of ARS was impossible because of dead time.
• New SAM chip same functionalities than ARS but
  with extended dynamic range, faster readout,
  higher bandwidth, higher depth and capability for
  2GS/s operation.
• MATRIX structure, 2 channels of 256 cells.
• Designed in 2004 on AMS CMOS 0.35µm technology.
  Ready for production.
• Nearly same architecture for the FE Board, but
  with an extra FIFO and more computation power in
  the FPGA.

1 SAM a new GHz sampling ASIC for the
H.E.S.S.-II Front-End Electronics., E. Delagnes
et al, Proceedings of Beaune Conference. to be
published in NIM. Preprint available on request
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The SAM chip block diagram
60000 transistors. 11 mm2
Need very few external signals to work (ltgt from
MATACQ). Many modes configurable by slow-control
(special modes, testability). Includes a TDC with
LSB1/Fsample Auto-configuration _at_ power on
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SAM chip main performances
2 x less than the SPE Readout time in the ARS
lt
PMT-like pulse sampled _at_ 1GS/s In black single
acquistion. In grey 1000 superimposed
acquisition. Excellent timing precision (lt50ps
rms)
Linearity plot
SPE spectrum (12 cells) with a HESS PMT
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And now ??

• Several options all based on the SAM chip
• (Integrate a 12bit ADC in a SAM).
• Extend the SAM memory depth (to several 1000
  cells).
• Investigate the feasibility of reading the sum of
  X cells in one read-out clock cyclegt equivalent
  to the SPE mode in ARS.
• Short term interest of hadronic physicists at
  Saclay for a dead time free SAM able to work
  with a 100kHz trigger with internal
  derandomizing buffer
• Increase again the readout speed.
• Operate with simultaneous R/W in a SAM (à la
  ATLAS), or/and design a SAM with multiple banks.