Behavioral Buffer Modeling with HSPICE Intel Buffer

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Behavioral Buffer Modelingwith HSPICE Intel
Buffer

• 10-08-03

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Objective

• Demonstrate alternative HSPICE behavioral
  simulation methods.
• Can be used when the present features of IBIS
  models are insufficient.
• Can be used for pre-silicon feature design
  characterization in a system environment.

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Topics

• Behavioral Driver models
• Close gap between technology and IBIS
• Convergence Advisory
• Circuits with that use switches and G elements
  tend to be more susceptive to convergence
  problems.
• High speed differential behavioral buffer and
  input characterization is an extension of these
  methods

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Simple CMOS Model
Rp

• Components
• Complementary Pulse source
• Switch
• Resistor
• Capacitor
• DC source
• Ground

Rn
Cn
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Assignment - 1

• Create simple CMOS model
• Use Pspice
• Rp10 ohm, Rn10 ohms
• Adjust Cn to get a 1 ns risetime (20 to 80)
  with a 50 ohm load and 1pf tied to ground
• Hint Use a 100MHz, 50 duty cycle for the pulse
  source.

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Behavioral Model Test Program

• Start with testckt file from pervious class
• MYBUFF will be our new generator
• DATAS will modified for different rise and fall
  times.

DATAS
Printed WiringBoard
Data generator
package
package
Buffers
Receiver
MYBUF
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Level 1 Behavioral Model
Vdd
01001100
Profile conditioner
PWL source
Buffer Pad
Profile conditioner
Math Process to create edges
DATAS
MYBUF
Vss
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Data pattern generator

• Syntax changed to yield different bit waveforms
  with different rise and fall times.

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Bit data waveform
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Creating a simple equation based V-T wave
01001100
pulse(t)
bits

• The bit pattern is used to create a
  representative PWL data wave.
• A proportional unity driving waveform (v-t wave)
  is created out of the PWL pulse.
• The edge of the ramp of the PWL pulse is
  proportional to the time for the bit transition.
• The entire transition of the pulse is related to
  the rise/fall time of the wave.

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Syntax HSPICE for driver
The circuit is completed with the voltage profile
derived from the unity driving waveform which
controls a dependant resistor tied to the n and p
loads. In this case the loads are 50 ohms. We
need to insure we dont divide by zero and also
do not result in an exact 0 ohm resistance.
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Convert the n p resistors to I/V devices

• The next task is to create I/V subciruits IVN
  and IVP
• To do this we use voltage controlled current
  source (VCCS)
• The G element is a piecewise linear (PWL) VCCS
• To create a I/V device, the control nodes and the
  output nodes are shorted

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I/V subcircuit example

• The columns are voltage on the left and current
  on the right
• This forms a table based I/V device since the
  control voltage imposed and current are across
  the same nodes

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If rising and falling edge shape differs, another
method is required

• If the bit pattern is not known a priori,
  controlling positive and negative shapes
  independently is difficult.
• In the previous example we controlled only slew
  rates not shapes.
• Will describe how to do this for the 2nd order
  buffer
• We will use the pulse source created as homework
  for the first HSPICE class.
• The edge for the pulse, if scaled correctly, can
  be made equal to the time of the bit transition.
• This is an important concept

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Level 2 Behavioral Model Block Diagram
simplify
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Simplify for example
Vdd
I-V
Profile conditioner
Fall
V-T
Writeenable
Buffer Pad
Rise
Bit Pattern
Voltage-Time Profile Generator
Profile conditioner
V-T
I-V
Vss
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Voltage-Time Profile Generator
RisingVT
Delay falling edge by falling edge transition
time
Positive Edge VoltageProfile Generator

• Voltage controlled voltage source
• Ramp voltage used to look up output voltagebase
  on v-t table

RisingVolt - Time RampGenerator
FallingVolt - Time RampGenerator
Negative Edge VoltageProfile Generator
Data in
FallingVT
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Voltage Time Ramp

• The voltage-time ramp is a ramp that starts at a
  specified time and whose voltage is proportional
  to the time from the specified starting point.
• In our case, we will create a voltage-time ramp
  on the detection of each bit edge transition.

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Explore the voltage across a capacitor

• If current, I is constant and is equal to the
  capacitance, then the voltage across the
  capacitor is equal to time.
• If the I does not equal C, the voltage is across
  the capacitor proportional to I/C.

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Define Characteristics of voltage time ramp
relative t0
Timet1
V
v1I/Ct1
t

• A unity voltage time ramp is when I/V 1 so that
  t1v1
• Since this voltage is usually small, I/C may be
  set to 1e9. This means 1 nanosecond corresponds
  to 1 volt.

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Circuit to create unit ramp

• The one input of a differential amp is connected
  to a dc reference and the other input is our
  input pulse wave.
• The switch shorts the cap at t0 and opens when
  the edge is detected.

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Delay falling edge .. digitally well almost

• Since we will use a threshold detector to
  determine an edge, we can add signals together
  and only use the portion of the signal that we
  deem important.
• Triggering at the reference threshold delays the
  negative edge

Threshold
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Put the circuit together for positive edge ramp.

• The processed signal is used to drive the switch
  which in turn creates the positive edge ramp.

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Put the circuit together for negative edge ramp.

• The negated data is used to drive the switch
  which in turn creates the negative edge ramp.

in
1 V
1 pA
In negated
out
1 pF
THRESHOLD_0_1_DETECT
X
1nV 1 nS after positive edge
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Positive Voltage-Time Ramp Generator HSPICE
CODE
delay in by tf Edelay in_delayed 0 DELAY in 0
TD'tf' create step shaped waveform for
delaying by tf Equalify_r edge_in_progress 0
VOL'V(in)V(in_delayed)' switch on edge in
progress is above 0.5 v Gswitch_r shunt_c_r 0
VCR PWL(1) edge_in_progress 0 .5v,.00001
.501v,1g Vone_volt one_volt 0 100v charge
rate is 1v/ns (I/C) Ccharge_r shunt_c_r 0 1pf
Icharge_r one_volt shunt_c_r 1ma
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Negative Voltage-Time Ramp Generator HSPICE CODE
Create complement of in Eneg_in in_bar 0
vol'1-v(in)' switch on edge in progress is
above 0.5 v Gswitch_f shunt_c_f 0
VCR PWL(1) in_bar 0 .5v,.00001 .501v,1g
charge rate is 1v/ns (I/C) Ccharge_f
shunt_c_f 0 1pf Icharge_f one_volt shunt_c_f
1ma
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Map ramp to V-T data with

• By driving the ramp into the control node of
  equation controlled voltage source, time on the
  ramp is mapped to voltage.
• This control voltage ranges from 0v to 1V is
  geometrically similar to the desired edge

relative t0
V
txvx
t
relative t0
V
txvx ? V(v)V(t)
t
Edge rate
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Mapping with PWL VCVS
This is the data for the corresponding edge shape
Time is scaled to the edge rate
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Putting edge together with v-t data
Voltage Controlled Voltage Sources
Rising V-tcurve
.SUBCKT VT_RISE_GEN_mid_n in out out_ref
Edatar out out_ref PWL(1) in
0 '0.000Tr_mid_n' 0.000 '0.185Tr_mid_n' 0
.006 '0.315Tr_mid_n' 0.017 '0.398Tr_mid_n' 0
.030 ... '0.917Tr_mid_n' 0.988 '0.944Tr_mid_
n' 0.994 '0.991Tr_mid_n' 0.999 '1.000Tr_mid_
n' 1.000 .ENDS VT_RISE_GEN_mid_n
Fall time
P
.SUBCKT VT_FALL_GEN_mid_n in out out_ref Edatar
out out_ref PWL(1) in 0 '0.000Tf_mid_n' 1.0
00 '0.023Tf_mid_n' 0.996 '0.034Tf_mid_n' 0.9
85 '0.057Tf_mid_n' 0.957 '0.739Tf_mid_n' 0.
016 '0.773Tf_mid_n' 0.008 '0.841Tf_mid_n' 0.
003 '0.989Tf_mid_n' 0.000 '1.000Tf_mid_n' 0.
000 .ENDS VT_FALL_GEN_mid_n
Falling V-tcurve
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Behavioral methods can be expanded to include new
features
Dynamic Clamp
Vdd
Clamp V-I Table
Writeenable
Buffer Pad
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Voltage-Time Profile Generator Review
PositiveV - T (voltage)Wave0-1V
Delay negative edge by negative edge transition
time
Positive Edge VoltageProfile Generator
PositiveVolt - Time RampGenerator Vtime
after edge

• Voltage controlled voltage source
• Ramp voltage used to look up output voltagebase
  on v-t table
• Caveat any ramp value gt edge time returns 1 volt

Bit Pattern
P
NegativeVolt - Time RampGenerator Vtime
after edge
Negative Edge VoltageProfile Generator
NegativeV - T (voltage)Wave0-1V
Waveform Voltage Profile
P profile is the 180 degrees out of phase
compared to the N profile
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Voltage Profile Resistance Conditioner
Riv
Vout
Rvt
Goal Create V-T Profile that produces a
geometrically similar waveform at
Vout Limitation Loads need in the range of Rtcal
Voltage controlled resistor
Rtcal
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Assignment 2 Create HSPICE Buffer Model

• Rp 100 ohms, Rn10 ohms
• Rise time 20-80 1.5 ns when driving a 50 ohms
  load ground
• You need to adjust the pulse transition time
• You should use sweep results in you report.
• Use wave shape as follows
• '(1-exp(-1(pwr(abs(v(in))2.4,wf))))'
• wf2, v(in) is pulse wave
• Vcc 2.5 V, Vss 0 V
• Check simulation against calculations of Vol and
  Voh with 50 ohm to Vss load

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Key Techniques To Remember

• Unity time voltage ramp
• PWL Voltage control voltage source creates V(t)
  edges.
• Simple buffers can be created by using switches
  in place of voltage controlled resistors.