Preliminary%20Design%20of%20Calorimeter%20Electronics

1
Preliminary Design of Calorimeter Electronics

• Shudi Gu
• June 2002

2
CsI Crystal

• 9864 CsI crystals
• 2 PIN photo diodes each crystal
• 0.8fc/MeV sensitivity
• CsI crystal resolution

3
Operation Conditions Specifications
System clock 20MHz
L1 trigger latency 3.2ms
Single channel event rate 1KHz
Range of charge 0.5fc1500fc
Resolution of charge (Energy) 0.16fc (200KeV)
Number of channel 9864
Integral nonlinearity 1 (before correction)
Cross talk 0.3
Dynamic range 15Bit
Information to trigger Analogue sum of 8 channels
Gain adjustable on line 20 nonuniformity
4
Block Diagram
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Preamplifier

• Low noise charge sensitive amplifier
• 1 AMP/diode, 2 AMPs/crystal
• Average of 2 AMP outputs to improve S/N
• Average of 2 AMPs or one of the 2 AMPs can be
  selected by jumpers on Post AMP when one AMP
  fails
• Calibration circuit at the input
• 20 wire twisted cable/Ch to Post AMP

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Preamplifier Specification
Gain 1mV/fc
ENC 0.16fc (80pf input capacitance)
Dynamic Range 0.5fc 1500fc
Output decay time 50ms
Max linear output 2V
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Post Amplifier

• ½(AB), A, B can be selected
• CR-(RC)2 with pole-zero cancellation shaping,
  t1ms
• Gain adjustable with digital potentiometer
• Analogue sum for trigger
• Differential connection with Pre-AMP and Q module

8
Q Module

• 3 FADCs sample signals from 3 different gain
  AMPs
• Delay samples with pipeline to wait for 3.2ms
  trigger latency L1
• Find peak during 2.5ms after L1 arrival
• Select peak, make range encoding compression,
  store data in buffer
• Inner trigger for radiation source calibration
  adjusting gain
• 9U VME module, 32ch/module

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Three Range Digitization
Range
Gain
Full Scale
Min. Energy
Digital Res.
CsI Res.
Res. Increa.
High
0.25
2.5Gev
0.625Gev
1.410-3
2.110-2
0.2
Middle
1
0.625Gev
0.078Gev
2.310-3
2.910-2
0.3
1.110-3
3.710-2
0.04
8
20Mev
Low
0.078Gev
0.6Mev
3.510-2
7.310-2
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• Three 10Bit FADCs with 3 ranges to get 15Bit
  dynamic range from 0.08MeV to 2.5GeV
• Small resolution degradation due to digitization

10
System Dynamic Range

• Dynamic range of digitization is wider than the
  charge measurement range
• Charge measurement precision is not infected by
  noise and digital resolution seriously

11
Test Controller

• Fan out and send 20MHz clock, L1 and L1 reset
  from trigger system to Q modules in the same
  crate for collision mode
• Generate 20MHz clock, L1, DAC and Test pulse for
  calibration mode
• Generate 20MHz clock for inner trigger mode. Test
  system with radiation source
• Generate 20MHz clock, serial clock and data for
  gain adjustment mode

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Local Buffer Readout

• Separate VME addresses and buffers for trigger
  number, Hit Map and data of 32 channels
• Only read channels pointed by Hit Map
• OR
• Read all channels without compression with
  Linked List DMA
• Enough readout speed with Linked List DMA
• A Q module for testing is designing with local
  buffer

13
Global Buffer Readout

• Controller on board moves compressed data from
  local buffers to a global buffer
• Read data from the global buffer with Direct DMA
• Higher speed but more difficult to design debug
  than local buffer
• Final Q module will be designed with global buffer