Conception d

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Conception dun processeur DSP faible énergie en
logique ternaire

• O. SENTIEYS, M. ALINE, E. KINVI-BOH

Université de Rennes - ENSSAT IRISA
sentieys_at_enssat.fr
FTFC 2003, Paris, 14-16 Mai 2003
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Outline

• Motivations
• MVL implementation with SUS-LOC
• Principle of SUS-LOC structures
• Characterization at the transistor-level
• Characterization at the gate-level
• Design of a ternary DSP structure
• Experimental results and comparisons
• Conclusion and future works

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Multiple Valued Logic (MVL)

• Currently, computers and other electronic devices
  run as 101101 binary logic with 2 logical
  states 0, 1
• MVL can offer
• Many logical states 0, 1, 2, 3,
• More complex functions
• in less time, power and area than binary ?
• MVL circuit structure ?

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MVL Circuits Structures

• Current-Mode CMOS Logic (CMCL) 3
• Voltage-Mode nMOS technology 16
• QCD or CCD technology 12
• Supplementary Symmetrical Logic Circuit Structure
  (SUS-LOC) 811
• Voltage-Mode (i.e. CMOS)
• Energy Efficient

• A new promising structure

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Technical advantages of SUS-LOC MVL circuits and
devices

• A decrease of passive parasitic values
• A decrease in required power (dynamic and static)
• Ability to perform multiple logic functions in
  one operation
• e.g. (AB) AND D
• Security, confidentiality

• An increase in data density
• Interconnections
• e.g. 40 bits become 25 terts1 (37.5 reduction),
  or 20 4L-digits
• More bandwidth with a reduced clock rate
• 16 bits f? 10 terts
• 1 Mbit/s ? 750 ktert/s
• Reduced package size

1 terts stands for ternary digits
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SUS-LOC structures
SUS-LOC principle
Transistor library
Characterization Process

• Principle
• Ternary case radix r 3
• Logic states 0,1,2
• r-1 different sources of power
• e.g. 0V, 1.25V, 2.5V
• r-1 independent controllable paths

VHDL Performance modeling
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SUS-LOC structures
SUS-LOC principle
Transistor library
Characterization Process

• Example ternary inverter
• Truth Table
• N(x) lt2 1 0gt

VHDL Performance modeling
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Transistor Library
SUS-LOC principle
Transistor library
Characterization Process

• Use of depleted and enhanced MOS
  transistors
• SPICE models
• 0.25m technolgy
• 2m SOI technolgy (UCL)

VHDL Performance modeling
Id(Vgs)
MbreakPD
MbreakND
MbreakP
MbreakN
MbreakP
MbreakN
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Logic Functions
SUS-LOC principle
Transistor library
Characterization Process

• Ternary CGAND
• Complementing Generalized AND
• CGAND(X,Y) N(MAX(x,y))

VHDL Performance modeling
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CGAND
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CGAND
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Characterization
SUS-LOC principle
Transistor library
Characterization Process

• Transistor-level Validation
• Delay and Power Characterization

VHDL Performance modeling
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Characterization
SUS-LOC principle
Transistor library
Characterization Process

• Transistor-level Validation
• Delay and Power Characterization
• e.g. Ternary vs Binary Inverter

VHDL Performance modeling
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Design of a ternary standard cell library

• CGAND, CGOR, Inverters,
• Mux, Tri-state
• LATCH, D Flip-Flop
• SRAM memory cell and sense amp.
• Arithmetic components
• HA, Pi, Gi, CLA, multiplier
• 1T-Shifter

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Gate-level
SUS-LOC principle
Transistor library
Characterization Process

• VHDL package for simulation
• STD_TERNARY_LOGIC
• VHDL set of tools for architecture- and
  gate-level estimations
• Power, Delay
• Gate-level simulation

VHDL Performance modeling
ELDO simulation Report file
VHDL Package
Power consumption Delay
VHDL Gate level simulation
Description.vhd
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Outline

• Motivations
• MVL implementation with SUS-LOC
• Design of a ternary DSP structure
• Experimental results and comparisons
• Conclusion and future works

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A ternary vs. binary DSP
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Interconnections

• Bus structure
• 16 bits become 10 terts
• 40 bits become 25 terts
• Activity of wires
• Binary
• Ternary

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SRAM Memory

• Transistor equivalent, faster access time
• Up to 50 in energy reduction

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SRAM Memory
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Arithmetic structures

• e.g. 40-bit vs. 25-tert Sklansky Adder
• 100 vs. 54 Brent and Kung cells

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Arithmetic structures

• e.g. 40-bit vs. 25-tert Sklansky Adder
• 100 vs. 54 Brent and Kung cells

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Other Structures
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Conclusion and future works

• SUS-LOC concepts for a ternary DSP
• Experiments on representative modules
• Comparison SUS-LOC vs. CMOS circuits
• High energy efficiency
• Future works
• Prototype chip with an SOI technology
• 3L and 4L SRAM and Flash memories
• Optimization of arithmetic structures

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Test Vectors
Schematic Netlist
Results
Characterization Process
Power, Delay Time
Simulation VHDL (Synopsys)
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Id F(Vgs)
Id
MBREAK P
MBREAK ND
MBREAK PD
MBREAK N
Vgs
V'tn
Vtp
Vtn
V'tp
0
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CGAND
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SUS-LOC structures

• List of some designed cells
• Inverter function N(x)lt210gt
• C0lt200gt, C1lt020gt, C2lt002gt
• CGOR(x,y)N(MAX(x,y))
• 2-input multiplier M(x,y)xy
• M(x,y)xy
• M(x,y, Cin)(xy)Cin
• Ternary half-adder
• THA(x,y,Cin)xyCin
• 2- or 3-input multiplexers
• Optimized adders structures
• Ternary SRAM