Advanced Digital Circuits ECET 146 Week 2

1
Advanced Digital CircuitsECET 146Week 2

• Professor Iskandar Hack
• ET 221G, 481-5733
• hack_at_ipfw.edu

2
Weeks Goals

• Downloading and Installing Alteras Quatrus
  Software
• Introduction of Alteras Quatrus II Software
  including
• Entering Design into Design Software using
  Schematic Editor
• Compiling design to implement into an Altera
  CPLD
• Reviewing Report File to Determine
• Chip Utilization
• Pin outs
• Simulating Design

3
Can you download Altera??

• The file is approximately 1.4 Gbyte and if you
  dont have a broadband connection dont attempt
  to download the file at home.
• Your options are (if you want to have the
  software installed at home or on a laptop) to
  bring in a blank CD to the lab tech office and
  request a copy or to use a large (2G or larger)
  flash drive and download it in the lab.

4
Downloading Alteras Max Plus II

• Go to Alteras University Download page at
  https//www.altera.com/support/software/download/a
  ltera_design/quartus_we/dnl-quartus_we.jsp Select
  Quartusii_50_sp_web_edition_single.exe

5
Downloading Altera Quartus II

• Fill in the questionnaire and submit request

6
Downloading Altera III

• Select Save File when download dialog appears

7
Downloading Altera III

• Select a directory that you will remember to save
  the file to (Firefox likes to save things to the
  desktop)

8
Installing Altera

• Open the directory you saved the install file to
  in Windows Explorer and double click the install
  file

9
Installing Altera II

• Accept all of the defaults when installing the
  software.

10
Installing Altera III

• Enter your name and either home or Purdue for
  when asked

11
Installing Altera IV

• Select Complete install

12
Installing Altera V

• Typical install screen

13
Installing Altera VI

• Turn off Talk Back when prompted

14
Entering Schematic Design

• Open the Altera Quatrus II Software and select
  new and then Block Diagram/Schematic file

15
Entering Symbols

• Draw the schematic by double clicking and
  selecting the symbols to enter appropriate
  symbols (note if you are entering more than one
  of the same symbol, you can turn on Repeat insert
  mode)

input (name of symbol
Repeat mode
16
Entering Wires

• Draw wires by moving the cursor over the inputs
  or outputs of gates (or I/O pads) until a
  crosshair appears (along with the upside down L)
  and draw with the left mouse button.

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Exercise One

• Draw the following schematic

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Renaming Pins

• Double Click on I/O pins show that they are
  highlighted and type in new name (the software
  should automatically highlight the next input pin)

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Finish Drawing for Exercise One

• Rename all the pins as shown

20
Save Design

• Go to File and select save as and save design as
  Example1.bdf (note gdf block design file) on
  your flash or zip drive if in lab, or in your
  working directory otherwise. Note, check box
  create new project based on this file

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Creating the Project I

• Say yes to the following dialog box

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Creating the Project II

• This page is just for information hit next

23
Creating the Project III

• Take the default on the next dialog box note the
  name of the project is the same as what you named
  the file. At this point (for this example) we are
  done we can hit Finish

24
Verify the Project is correct

• After setting the project be sure that that the
  project name matches the file name.

Project Name
Current File being edited
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Notes regarding Project Names

• The project name does NOT contain the .bdf
  extension
• Thus if there are more than one type of design
  file in the project such as wdf (waveform design
  files) or tdf (text design files) then the system
  will not know what file goes with the project
  name.
• Therefore you can NOT have a file named
  Example1.bdf and Example1.tdf in the same
  directory. This will cause MAJOR problems for the
  software.
• Later in the semester youll have projects with
  more than one file BEWARE of the names of the
  files, they must be unique.

26
Compiling the Project

• Hit the hot key on the top of the screen to start
  compiling your project.

27
The Compiler

• If you did everything right thus far you should
  see something like this

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Compiler Reports

• The compiler creates a number of reports, which
  at this point would mean nothing to you, but you
  may want to explore them.

Boolean EQ
I/O pin info
29
Drawing Waveforms for Simulation

• We now need to create a new file to hold our
  simulation input waveforms. This done by hitting
  new and selecting Other and vector waveform file
  (vwf)

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Entering Nodes

• You will need to double click in the node area of
  the display this will bring up the following
  dialog box

Select Node Finder
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Entering Nodes II
(1) Start by selecting Pins all
(2) Then hit List
(3) Move all pins to the right by hitting gtgt
(4) Hit OK
32
Check if all nodes are selected

• Verify in the waveform editor that all nodes are
  shown

Inputs
Output
33
Change Grid and End Time

• Select Edit, Grid time, and change it to 50 nS
• Select Edit, End time and change it to 1.6 uS

34
Grouping Inputs

• Select all the inputs, right click, hit Group
  and use inputs3..0 for the name of the inputs,
  Hex as radix, and uncheck grey count

35
Display after Grouping
will expand group to show the individual
pins - will hide individual pins
36
Using Count Function

• Select the Group, and then hit the count button
  on the left side of the screen. Take the defaults
  (start at 0, incr by 1, End value F)

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Display after Count

• You should see the following after hitting OK

38
Save Simulation File

• Up to now you should have seen that the output is
  neither high or low. That is because it has not
  been simulated yet.
• In order to simulate you must first save the file
  as example1.vwf

Leave checked
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Simulate

• This is the easy part Hit the simulate button
  on the top of the screen.

Simulate
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Verify Simulation

• You should have a value for the output for each
  input condition.
• Manually determine (using techniques from ECET
  111) what the output should be for each condition
  and verify that the output matches that.

41
Simulation Display
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Assignment One

• Using techniques from ECET 111 design a circuit
  (no need to minimize) for the following Boolean
  expression.
• Manually draw up truth table for the equation
• Enter the design into the Altera Software and
  simulate the design
• Youll need to use the following symbols
• NOT
• AND2
• OR2
• INPUT
• OUTPUT
• Compare the truth table to the simulation
• Turn in hand drawn schematic, truth table, print
  out of the schematic from Altera, and a copy of
  the simulation.