Power and Complexity Aware Microarchitectures - PowerPoint PPT Presentation

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Power and Complexity Aware Microarchitectures

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U. P. C. Power and Complexity Aware Microarchitectures. Jaume ... Resize dynamically the ROB and issue queue according to their occupancy. Dependence Based IQ ... – PowerPoint PPT presentation

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Title: Power and Complexity Aware Microarchitectures


1
Power and Complexity Aware Microarchitectures
  • Jaume Abella1
  • jabella_at_ac.upc.es
  • http//people.ac.upc.es/jabella
  • Ramon Canal1
  • rcanal_at_ac.upc.es
  • http//people.ac.upc.es/rcanal
  • Antonio González1,2
  • antonio_at_ac.upc.es
  • http//people.ac.upc.es/antonio

2
Issue Logic (I)
  • Adaptative IQ
  • Resize dynamically the ROB and issue queue
    according to their occupancy
  • Dependence Based IQ
  • Keep direct relationships between producer and
    consumer
  • Prescheduling IQ
  • Schedule instruction issue according to the
    latencies of functional units

Power-Aware Adaptive Issue Queue and Register
File, HiPC 2003
A Low Complexity Issue Logic, ICS 2000
Reducing the Complexity of the Issue Logic, ICS
2001
3
Issue Logic (II)
  • FP distributed issue queue without CAM cells
  • Dispatch
  • Instructions belonging to a dependence chain are
    sent to the same queue
  • Multiple dependence chains may share a queue
  • Issue
  • Small table keeps track of how many cycles has to
    wait the first instruction of a chain to be
    issued
  • First, select the oldest instruction that will
    become ready next cycle. Second, the oldest ready
    instruction

Low-Complexity Distributed Issue Queue, HPCA
2004
4
Memory Hierarchy
  • Heterogeneous L1 Dcache banks
  • Adaptative L2 Cache
  • Deactivate Cache Lines
  • Current predictors are L1 cache oriented
  • L1 and L2 behave quite different
  • Use access counts and inter-access time to
    compute decay intervals

L2 cache
Slow cache
Fast cache
L1 First access
Hit Hit Hit Hit
Replaced
Is critical?
L2 First access
YES
NO
Hit Hit Hit
Replaced
LOAD
Power Efficient Data Cache Designs, ICCD 2003
Smart Predictors to Turn-off L2 Cache Lines,
under submission
5
Hw Value Compression
32-bit embedded processor pipeline with value
compression
  • Dynamically compress values flowing through the
    pipeline
  • Good for embedded and high performance
    processors!!

Very Low Power Pipelines using Significance
Compression, MICRO-33
6
Compiler directedValue Compression
After Value Range Specialization
Original Code
Narrow operations according to its operands
compression
Duplicate and specialize certain regions of code
Software-Controlled Operand-Gating, CGO 2004
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