AUSTIN CONFERENCE ON

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• AUSTIN CONFERENCE ON
• ENERGY-EFFICIENT DESIGN
• March 1-3, 2005

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Thanks!

• ACEED Committee Chairs
• Bruce Knaack (General Chair), Karthick Rajamani
  (Program Chair), Soraya Ghiasi (Organizing
  Chair), Pradip Bose (Technical Program Chair)
• ACEED Technical Program Committee
• Emrah Acar, Pradip Bose, Thomas Bucelot, Gary
  Carpenter, David Chambliss, Brian Curran, Lee
  Eisen, Nick Gruendler, David Hathaway, Tom
  Keller, Stephen Kosonocky, Toshio Nakatani, Kevin
  Nowka, Freeman Rawson, Anthony Saporito,
  Vijayalakshmi Srinivasan, Victor Zyuban,
• ACEED Organizing Committee
• Soraya Ghiasi, Tom Keller, Bruce Knaack, Christa
  Mace, Marisa Mace, Kathy Nix, Kevin Nowka,
  Karthick Rajamani, Heather Wagner
• Attendees and presenters

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Overview

• Presentations
• 43 papers submitted
• 20 regular papers accepted
• 21 posters (external session)
• 17 posters (internal session)
• Attendance Day 1 138, Day 2 103, Day 3 - 98
• Universities Carnegie Mellon University,
  Princeton University, University of Illinois at
  Urbana-Champaign, University of Erlangen at
  Nuernberg, University of Colorado, Purdue
  University, University at Buffalo, Texas AM,
  University of Texas at Austin, University of
  Texas at San Antonio, University of Virginia
• External corporations Sony, Intel, Science and
  Technology Associates, Texas Instruments
• IBM Research (Almaden, Austin, Haifa, Tokyo,
  T.J. Watson labs), Austin Center for Advanced
  Studies, Systems and Technology Group, Corporate
  HQ, STI

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IBM Research Worldwide
Watson Yorktown Heights, NY
Zurich R?schlikon, Switzerland
China Beijing, China
Almaden San Jose, California
Austin Austin, Texas
Tokyo Yamato, Japan
India Delhi, India
Haifa Haifa, Israel
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Systems Will Be Designed With the Ability to
Dynamically Manage and Optimize Power
Power densities of all system-level elements
(device to rack) are increasing exponentially

• Power dissipation is increasingly limiting the
  performance of processors and systems driving new
  design techniques
• The power of high-end processor chips has
  exceeded 200 Watts
• Blades will push the power to 5 KW/sq-ft within
  the next 5 years
• Costs for cooling data centers will increase
  significantly
• Future systems will need to dynamically manage
  power at runtime
• Ability to quickly turn system elements on/off,
  control frequency including microprocessors,
  caches, memory and busses

Power distribution of an IBM midrange server
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Why Systems Level Power Management?
Power is now 1st class design constraint across
the computing spectrum Power densities of all
computing components at all scales are
increasing Power consumed by every component in
the system needs to be addressed. Process and
workload variation limit the scope of static
solutions Our approaches Exploit real-time
measurements to guide power and thermal
management. Use continuous system performance
and utilization monitoring to exploit load
characteristics for effective distribution of
available power and maximization of
performance. Understand time-varying power and
thermal characteristics of components under real
loads and develop techniques to guide adoption of
dynamically adapting solutions - self-tuning
systems. Develop new techniques to budget and
manage power in very high-utilization systems.
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System Level Power Management Interfaces
Rack/Chassis Hardware
Capacity Planning
Enterprise-Level Management (Tivoli, )
Group-Level Management (IBM Director,)
Measurement Data
Management Module
Query/ Calibration
Reference Inputs
Control Parameters
Measurement Data
Hypervisor/OS
Master
Service Processor
Query/ Calibration
Restricted
Measurement Data
Get/Set State
Set Power States
Sensor Data Power, Thermal, Board Fans,
Virtualization Boundary
Facilities Management (Power, HVAC,)
System Hardware
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Summary

• Power is now a 1st class design constraint across
  the computing spectrum
• Designers choose power constraints and then
  optimize for performance
• Power efficiency enables leading edge system
  design and is a differentiator
• No silver bullet solution
• System level power management across the entire
  IT complex
• Process technology
• Transistor materials
• Power aware microarchitectures
• System/hypervisor power management
• IT room power management
• Enterprise level power management
• Core, board, chassis, room monitors/control
  points

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• 0800 - 0825 Coffee Reception and Sign-In
• 0825 0830 Welcome
• Bruce Knaack, Aceed 2005 General Chair
• 0830 - 0845 Opening Remarks
  Lorraine Herger, Director, Austin Research
  Laboratory
• 0845 - 0930 IBM Keynote George Chiu, Senior
  Manager, Advanced Server Hardware Systems
• 0930 - 1010 Efficient Power Consumption in the
  modern Datacenter William Hammond, Intel
• 1010 - 1030 Break
• 1030 - 1110 Adaptive Power/Performance
  Management for High-end Microprocessors Margaret
  Martonosi, Princeton University
• 1110 - 1150 Understanding Nanoscale
  Devices Supriyo Datta, Purdue University
• 1150 - 0200 Lunch Break and Poster Session
• 0200 - 0240 Leakage and leakage control
  techniques for Nanoscale CMOS Device Circuit
  Perspective Kaushik Roy, Purdue University
• 0240 - 0320 Energy Awareness and Uncertainty in
  Design at Microarchitecture Level Diana
  Marculescu, Carnegie-Mellon University
• 0320 - 0340 Coffee Break
• 0340 - 0420 Event-Driven Energy Accounting for
  Internet Data Centers Frank Bellosa, University
  of Karlsruhe
• 0420 - 0500 Power-Efficient Microarchitectures
  Krste Asanovic, MIT
• 0500 - 0600 Panel Session The role of power
  management in maintaining the growth of the
  computing industry Panelists Carl Anderson, IBM
  (moderator) Krste Asanovic, MIT Frank Bellosa,
  University of Karlsruhe George Chiu, IBM Bob
  Dennard, IBM and Margaret Martonosi, Princeton
  University
• 0600 - 0615 Concluding Remarks Bruce Knaack,
  Energy Efficiency Institute Program Director, IBM
  Austin Research Laboratory
• 0630 Bus departure from Conference Site to
  Dinner Site
• 0730 Dinner