The DLX Implementation

1
Instruction Set Architecture

• simplified DLX A RISC architecture with only
  two instruction formats.
• 32 general purpose registers, each 32 bits wide
  R0-R31.
• Register R0 always stores the value of 0.
• Load and Store operations move data between the
  general purpose registers and
• the main memory.
• All instructions are represented by a word 4
  bytes 32 bits.
• The DLX architecture also has a few special
  purpose registers mainly used for
• handling interrupts. Special move instructions
  transfer data between general and
• special purpose registers.

2
The Registers
Registers are clock-enabled flip-flops. Their
goal is to store binary data. The registers are
divided into two major groups
General Purpose Registers
Special Registers
In the General Purpose Registers
(GPR) environment
In the Special Registers environment
In other environments
3
The General Purpose Registers

• The General Purpose Registers R0-R31
• The GPR environment contains 32 registers each
  32 bits long.
• Store data (arguments and results of
  instructions).
• GPR environment functionality in every clock
  cycle
• may read the values of 2 registers (values
  appear in A B).
• may write the value of 1 register (value given
  via C).
• implemented via a dual-port RAM.
• registers A,B,C are not part of ISA (they are
  part of datapath).

4
Special Registers

• Responsible for storing information that is
  essential for running DLX programs.
• List of special registers
• Program Counter (PC) - stores the address of the
  current instruction.
• Instruction Register (IR) - stores the current
  instruction.
• More Special Purpose Registers needed to
  support interrupt handling.
• Datapath registers (not part of ISA)
• Memory Data Register (MDR) - stores data that is
  written to the memory or read from the memory.
  The MDR holds data for store/load instructions.
• Memory Address Register (MAR) -stores the memory
  address that is accessed in load/store
  instructions.

5
The Instruction Formats
Two formats of instructions
R-Type (Register)
I-Type (Immediate)
Opcode, three registers an additional 6-bit
opcode (function)
Opcode, two registers a 16-bit constant
6 5 5 5 5
6
6 5 5 16
Opcode RS1 RS2 RD Function
Opcode RS1 RD Immediate
6
The Instruction Formats (Cont.)
Lets see some examples
Opcode RS1 RD Immediate
1) 001011 00110 01001 0000000000111111
This is an I-type instruction because IR3126
is not 000000.
001011 is the opcode of the addi instruction.
00110 is the binary representation of 6.
01001 is the binary representation of 9.
0000000000111111 2s complement representation
of 63.
representation 2s complement representation is
used for the immediate field and for the general
purpose registers.
The instruction is addi R6 R9 63 and in other
words R9 ? R6 63
Assembly
Semantics
7
The Instruction Formats (Cont.)
Opcode RS1 RD Immediate
2) 011010 00011 11001 0000000000000011
Again, This is an I-type instruction because
IR3126 is not 000000.
011010 is the opcode of the seqi instruction.
00011 is the binary representation of 3.
11001 is the binary representation of 25.
0000000000000011 2s complement representation
of 3.
The instruction is seqi R3 R25 3 and in other
words
Assembly
Semantics
R25 ?(R3 3) ? 1 0
8
The Instruction Formats (Cont.)
Opcode RS1 RS2 RD Function
3) 000000 00101 00111 01101 100011
This is a R-type instruction because IR3126 is
000000.
000000 is the opcode of the R-Type instructions.
00101 is the binary representation of 5.
100011 is the representation of the add
instruction.
The instruction is add R5 R7 R13 and in other
words R13 ? R5 R7
Assembly
Semantics
9
The Instructions Types
Several Types of instructions
Load/Store
Immediate
Shift/Compute
Test
Jump
10
Simplified DLX instruction set
11
What is the DLX?
From the programmers point of view (ISA) DLX is
a universal machine that executes programs stored
in the main memory written in the DLX
instructions set.
12
The DLX Implementation
The general idea
Fetch
IR MPC
Decode
decode the instruction stored in the IR. prepare
the operands from the GPR (if necessary)
Execute
A calculation (e.g. add, compare)
Increment PC
Memory Access
Memory access in load/store instructions
Write- Back
Store the result of the operation in
the destination register in the GPR Env.
13
The Datapath the Control
Datapath - A collection of functional units,
registers and multiplexers
connected by buses.
Control A state machine that manages operation
of functional units, drivers
that write to buses, clock-enable signals.
The Control produces signals whose name
is Control Signals.
Datapath
Control
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15
The DLX Commands Implementation

• General Remarks
• Execution of an instruction requires some clock
  cycles.
• Instructions do not have equal running time.

The DLX
The Control
The Datapath

• General Purpose Registers
• Functional Units (ALU)
• Main Memory (interface)
• buses

Controls the data flow in the datapath.

• Notes
• Very few Control states.
• Even in modern processors states lt 200.

16
A reminder What is the RAM?
RAM Random Access Memory The term Random
means that one may access any word (as oppose to
tape in which only next / previous word may be
accessed). The memory is modeled as an array of
words. The index of each word is called the
address of the word. Mi is the word stored in
the address of i.
17
A reminder What is the RAM (Cont.) ?
Input / Output ports
1
A bit indicating if reading or writing
RAM
Write
Adr.
Data in
Data out
The functionality is
Write 0 (Reading operation) Data out
MltAdr.gt Write 1 (Writing operation)
MltAdr.gt Data in Data out
Logical

18
Lets get deeper
In the following slides we will zoom into each of
the five types of Control states, describing what
happens in each type.
19
What happens during Fetch state?
Din
Adr
PC
Memory Env.
Was the mission completed?
W
MR
Dout
Busy
IR Env.
Control
IR
1) The PC register contains the address.
Sample!
2) The desired functionality IR MPC
3) The memory is very slow. It announces Im
busy after getting a read / write request. When
busy, no new requests are allowed. As Dout
stablizes, the memory announces Im done. Only
then the control asks the IR Env. to sample
Douts value and update the IR register.
The Control usually stays in fetch state for
more than one clock cycle
Fetch
20
What happens during Decode state?
The string dealt with is the one located in the
IR register and may be of two types
6 5 5 16
1) I-Type
Opcode RS1 RD Immediate
Adr. 1

• Determine
• I-Type?
• Next state.

General Purpose Registers (GPR) Env.
Sign-Extension
Read!
A B
A operand (Copy of RS1)
The constant (sign-extended)
21
What happens during Decode state (Cont.)?
6 5 5 5 5
6
A continuation of the Opcode field.
2) R-Type
Opcode RS1 RS2 RD Function
Adr. 1
Adr. 2
Not used

• Determine
• R-Type?
• Next state.

General Purpose Registers (GPR) Env.
Read!
A B
A operand (Copy of RS1)
B operand (Copy of RS2)
22
What happens during Decode state (Cont.)?
Notes

• IR2521 represent RS1.
• IR2016 represent RS2.

Opcode RS1 RS2 RD Function
2) The GPR Env. Is able to perform two read
operations at the same clock period (Dual Port
RAM).
3) The PC register is advanced in the decode
stage PC PC1. This is done in order to avoid
the use of another Control state and because this
increment can be done in the decode stage (buses
and ALU are free).
23
What happens during Execute state?
Some kinds of instructions

1. Instructions which use the ALU (Arithmetic
   instructions, Logic instructions and TestSet
   instructions)

A reminder
R-Type
I-Type
RD RS1 Sext(Imm) RD RS1 RS2 RD (RS1 gt
Sext(Imm) ? 1 0) RD (RS1 gt RS2 ? 1 0)
2 operands The first is always RS1 and the
second is either RS2 or Sext(Imm).
24
What happens during Execute state (Cont.)?
A. Arithmetic/Logic instructions
GPR Env.
C
IR Env.
Cce
A
B
Sext (Imm.)
1 0
ITYPE
ALU Env.
ALU Control signals
Result
25
What happens during Execute state (Cont.)?
B. TestSet instructions
Sgri RD (RS1 gt Sext(Imm) ? 1 0)
GPR Env.
C
IR Env.
Cce
A
B
Sext (Imm.)
1 0
ITYPE
Two stages 1) execute C (RS1 gt RS2 ? 10) 2)
writeback RD C In this way the period time is
shorter.
Always 0 / 1
ALU Env.
TEST
Result
26
What happens during Execute state (Cont.)?
2) Shift instructions These instructions are
always in R-Type structure.
Slli RD RS1 ltlt 1 Srli RD RS1 gtgt 1
The shift amount is 1
The word to be shifted is stored in RS1
GPR Env.
C
IR Env.
Cce
A
B
According to Func.
1
From The PC Env.
Shifter
Generally, the 1 constant may be any other
constant and the shift may be of more than one
place
RIGHT
Result
27
What happens during Execute state (Cont.)?
3) Jump instructions A. Unconditional jump
Jump Reg (jr) PC A
No direct path from A to PC. Instead
GPR Env.
IR Env.
A
0
ALU Env.
ADD
PC Env.
PC
Cce
28
What happens during Execute state (Cont.)?
B. Branch Jump only if a condition is
satisfied
beqz PC PC1(RS10 ? Sext (Imm.) 0)
bnez PC PC1(RS10 ? 0 Sext (Imm.))
Well demonstrate the beqz instruction. Two
states are needed
State I - Branch Check the condition RS10 ?
Sext (Imm.) 0
GPR Env.
IR Env.
A
0
ALU Env.
TEST
Comparison result
To the Control
29
What happens during Execute state (Cont.)?
The next state
Jump
No Jump
BTaken
Fetch
State II - BTaken Calculating the jump PC
PC1(Result of state I)
IR Env.
PC Env.
PC
Cce
PC
Sext (Imm.)
ALU Env.
ADD
30
What happens during Execute state (Cont.)?
C. Calling a routine Jump, remember your
address so it will be possible to get back
to this address
jalr R31 PC1 PC RS1
We use two Control states in order to execute
this instruction because we want to avoid a
collision in the buses (to be elaborated).
31
What happens during Execute state (Cont.)?
State I Copying the PC (2 clock cycles)
Clock cycle 1
GPR Env.
C
PC Env.
PC
Cce
Clock cycle 2 (like in the Write-Back state)
GPR Env.
C
Write!
The address31
R31
32
What happens during Execute state (Cont.)?
State II Calculating the jump address
GPR Env.
PC Env.
IR Env.
PC
Cce
0
A
ALU Env.
ADD
33
Reading From Memory - Load
Load Word (lw) RD M(Sext(imm.) RS1)
Four states are needed for finishing the load
instruction
State I Effective Address Computation MAR
AC0
GPR Env.
IR Env.
C0
A
Sext(imm.)
ALU Env.
ADD
MAR
Sext(imm.) RS1
34
Reading From Memory Load (Cont.)
State II Memory Access (Load). This state lasts
till the value is returned MDR M(MAR)
Adr
MAR
Memory Env.
Read!
W
Dout
Busy
Tells the Control when readung is over
MDR
Notes
1) Busy signal informs the Control when the
operation is over (Dout is stable).
2) MDR samples Dout every clock cycle, no need to
compute CE (Simplifies Control).
3) Dout must be logical even if its value is
incorrect!
35
Reading From Memory Load (Cont.)
State III Writing MDRs value to C in the GPR
C MDR
MDR
GPR Env.
C
Cce
State IV Write-Back RD C
36
Writing To Memory - Store
Store Word (sw) M(Sext(imm.) RS1) RD
Three states are needed for finishing the store
instruction
State I Effective Address Computation MAR
AC0
GPR Env.
IR Env.
C0
A
Sext(imm.)
ALU Env.
ADD
MAR
Sext(imm.) RS1
37
Writing To Memory Store (Cont.)
State II Copying the B registers (this is RD)
value to the MDR MDR B
GPR Env.
B
MDR
State III Memory Access (Store) M(MAR) MDR
MDR
Din
Memory Env.
Adr
MAR
Write!
Busy
W
Tells the Control when writing is over
38
Write-Back
The Write-Back stage occur in the following
instruction types
Arithmetic
Logic
Shift
Test Set
Load
In this stage, the following happens RD C
GPR Env.
C
Write!
RD
R0-31
RDs value is determined according to a
I-Type/R-Type structure. This is the reason
for having two different Write-Back states (WBI
WBR).
39
Write-Back (Cont.)
The RDs field may be either one of two
candidates, according to the instructions type
(I-Type/R-Type). The decision is based on the
string located in the IR register
5 5
IR
0 1
ITYPE
RD
The RD field possibilities