Recommending a Strategy

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Memory Hierarchy for Microblaze and PowerPC based
Systems
Under the guidance of Dr. Kolin Paul
Department of Computer Science and
Engineering IIT DELHI
Presented by Nikunj Shroff 2005JCA2435 .
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Agenda

• Objective.
• Project Overview.
• Core Block Diagram of MicroBlaze.
• SystemC.
• Block Diagram of system (PowerPC).
• Image Processing application.
• Observation.
• References.

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Objective

• Analyze the possibility of constructing a
  hierarchy of memories
• Different Capacities
• Different access times
• Develop Memory hierarchy for embedded system
  containing
• Microblaze (and / or) PowerPC processor
• Embedded RAM
• BRAM
• Distributed Ram

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Project Overview

• MicroBlaze
• Configuration of cache in Microblaze.
• SystemC
• Modeling of Microblaze
• PowerPC
• Configuration of cache in PowerPC.

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Processors

• MicroBlaze
• SoftCore
• Runs at 100 MHz
• PowerPC
• HardCore
• Runs at 400 MHz

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Microblaze Core Block diagram
MicroBlaze (www.xilinx.com)
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Cache link interface

• The MicroBlaze CacheLink interface
• Connect to an Fast Simplex Link (FSL) interfaced
  memory controller via an explicitly instantiated
  FSL master/slave pair.
• Connect directly to a memory controller with
  integrated FSL buffers, e.g. the MCH_OPB_SDRAM),
  which results in less latency and fewer
  instantiations.

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Data Cache

• All cacheable data addresses are further split
  into two segments
• Cache word address segment
• Tag address segment.
• The size of the two segments can be configured by
  the user.
• The size of the cache word address can be between
  11 to 14 bits. This results in a cache sizes
  ranging from 8 kB to 64 kB.
• The tag address should be sized so that it
  matches the complete range of cacheable memory in
  the design.

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Data Cache Operation

• If MicroBlaze executes a store instruction,
• If the address is not within the cacheable
  address segment
• Operation is performed as normal but
• If the address is within the cacheable address
  segment,
• Data cache is updated with the new data,
• Cache is not updated on a write miss.
• If MicroBlaze executes a load instruction,
• If the address is within the cacheable area,
• Whether the address is currently cached.
• Data is retrieved from the cache.
• If the address is not within the cacheable area
• Normal operation is performed

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Example

• E.g. assuming a configuration of
• C_DCACHE_BASEADDR 0x00400000, C_DCACHE_HIGHADDR0
  x00403fff,
• (All addresses within this range correspond to
  the cacheable address space segment. All other
  addresses are non-cacheable)
• The cacheable byte address range is 14 bits.
• C_DCACHE_BYTE_SIZE2048
• Cache byte address range is 11 bits (i.e. a 9 bit
  cache word address),
• Thus the required address tag is 14-113 bits.

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System View (when cache is not enabled)
Microblaze
BRAM
DLMB
DOPB
ILMB
IOPB
Timer
UART Controller
To UART
Memory Controller
To External Memory
Hardware Debug Module Controller
To XMD Debug Module
SOPB
OPB
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System View (when cache enabled on OPB Bus)
Microblaze
BRAM
DLMB
DOPB
Microblaze Trace IP (My Ip)
ILMB
IOPB
Timer
UART Controller
To UART
Memory Controller
To External Memory
Hardware Debug Module Controller
To XMD Debug Module
SOPB
OPB
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System View (when cache is enabled using Xilinx
cache link)
Microblaze
BRAM
DLMB
DOPB
Microblaze Trace IP (My Ip)
ILMB
IOPB
DXCL
IXCL
To UART
UART Controller
Memory Controller
MCH 0
MCH 1
To External Memory
To XMD Debug Module
Hardware Debug Module Controller
SOPB
Timer
OPB
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System View (when cache is enabled using FSL link)
BRAM
Microblaze
DLMB
DOPB
Microblaze Trace IP (My Ip)
ILMB
IOPB
1 2 3 4
FSL 0,1,2,3
UART Controller
To UART
Memory Controller
To External Memory
Hardware Debug Module Controller
To XMD Debug Module
SOPB
1. Fsl Data Cache In 2. Fsl Data Cache Out 3. Fsl
Instruction Cache In 4. Fsl Instruction Cache Out
Timer
OPB
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SystemC

• To create a system-level model.
• Quick simulation in order to validate and
  optimize the design.
• Provide the hardware and software development
  with an executable specification of the system.
• The SystemC Class Library provides the necessary
  constructs to model system architecture including
  
• Hardware timing,
• Concurrency, and
• Reactive behavior

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Top Level Design
Stored from a External File Inst.txt
Stored to and from local user defined Array
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Internal Architecture
MicroBlaze
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Microblaze
Microblaze
i_en
instr
i_address
To IBRAM
From IBRAM
i_fetch
i_ready
i_as
D_ready
en
From DBRAM
Data_read
Read_strobe
Write_strobe
To DBRAM
i_address
Byte_enable
address
Data_write
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Cache Memory Mapping
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Direct and Associative Mapping
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SYSTEM VIEW
FPGA
BRAM
OPB
PLB
ILMB
DLMB
PowerPC
Application BRAM
MicroBlaze
USB Connection
Timer IP (My IP)
PLB2OPB Bridge
UART RS-232
Memory Controller
OPB2DCR Bridge
Sys ACE Controller
DCR
Video Controller
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Logical portioning of memory
First Image
2 MB
Second Image
2 MB
2 MB
Third Image
256 MB External Memory
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Memory Hierarchy of the System
Registers (Internal to PowerPC / MicroBlaze)
BRAM Cache for PowerPC (fixed 16KB) Cache for
MicroBlaze ( variable size)
Main Memory 256 MB External DDR Memory
Flash Drive 256 MB
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Bitwise colors stored in memory location
Memory Location Blue Green
Red Unused 00000000 84 252 84
0 00000001 252 252 84
0 00000002 84 84 252
0 00000003 252 84 252
0 00000004 84 252 252
0 00000005 252 252 252
0 00000006 0 0 0
0 00000007 168 0 0
0 00000008 0 168 0
0 00000009 168 168 0
0 0000000A 0 0 168
0 0000000B 168 0 168
0 0000000C 0 168 168
0 0000000D 168 168 168
0 0000000E 84 84 84
0 0000000F 252 84 84 0
Blue Green Red Unused
0
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Image Processing
Normal image
Revert Color
Mirror Image
Mirror Revert
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Observation
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Overall Comparison
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Observation (PowerPC)
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Overall Comparison (PowerPC)
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Conclusion

• In case of small program used in Microblaze
• Instructions are fetched frequently so caching of
  instructions gives high performance gain.
• In above mentioned memory models xilinx cache
  link is the best one which has less latency for
  instruction and data access.
• In case of large program used in PowerPC
• The size of Data is more so caching of data in
  this case gives more performance gain.

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References

• Embedded Development Kit, Getting Started with
  EDK, 1-800-255-7778 EDK 7.1i February 15, 2005
  http//www.xilinx.com.
• MicroBlaze Processor Reference Guide,1-800-255-777
  8 UG081 (v5.0) January 20, 2005
  http//www.xilinx.com.
• FPGA Field Programmable Gate Array,
  http//www.andraka.com/whatisan.htm
• VHDL Very High Speed Integrated Circuit Hardware
  Description Language http//ghdl.free.fr/ghdl/inde
  x.html
• Fast Simplex Link FSL, DS449 December 1, 2005
  www.xilinx.com
• MCH controllerMulti-CHannel (MCH) On-chip
  Peripheral Bus controller. DS496 July 1, 2005
  www.xilinx.com
• PowerPC Processor. EDK 6.1 September 2, 2003
  www.xilinx.com
• Relocating Data and code for embedded systems,
  XAAP642 (v1.0) October 21, 2002
• www.xilinx.com.
• Platform studio User guide for EDK 6.2i UG113
  (v1.0) March 12, 2004

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Thank You ....!!