Low Temperature Spatially Resolved Digital SET in Deep Submicron CMOS

1
Low Temperature Spatially Resolved Digital SET in
Deep Submicron CMOS
Rad-13
Description
FY08 Plans

• This task can leverage off the fact that a
  similar task (laser based) already exists within
  JPL and will finish this fiscal year. Test
  structures (0.18mm TSMC) including single and
  multi-inverter chains with output nodes scaled to
  allow direct current measurement on a
  high-bandwidth system are fabricated.
• The high-frequency test boards designed for
  laser work are already available and ready for
  ion beam analysis. Laser results already underway
  can be used an be leveraged off a similar task.
  This funding can be used to
• extend some findings.
• Correlating struck location with the measured
  transient is a useful means of investigating the
  influence of structure etc on DSET propagation.
  The study will be performed against temperature.
• Beam time on both the SNL and JAEA microbeam
  lines will provide a useful comparison to laser
  results previously collected. This task may also
  discuss some issues raised in the NEPP 2006 task
  on microbeam feasibility.

• Digital Single Event Transients are becoming
  the dominant source of SEU in high-speed, highly
  scaled CMOS combinatorial logic. DSET
  characteristics at low temperatures are to date
  unknown.
• To date most techniques examining this issue
  have relied on an indirect measure of the pulse
  width. Test structures composed of various chains
  of inverters have been fabricated at TSMC (0.18mm
  technology) with output nodes scaled to allow
  direct transient current measurement using a
  pulsed laser and/or ion microbeam.
• The aim of this task is to pin-point sensitive
  regions in the inverter chain and directly
  measure the temperature dependence of the SET
  spatiotemporal response using a high-bandwidth
  measurement system on a pulsed laser system. The
  results will be compared to ion microbeam results
  at room temperature for normalization.

Schedule/Costs
Deliverables
Total Full-Cost

• NEPP report on the temperature dependence of
  DSET propagation in 0.18mm CMOS and possibly a
  general trend with scaling when combined with
  other reports in the community.

NASA and Non-NASA Organizations/Procurements
Lead Center/PI JPL Co-Is Yuan Chen
(JPL) Contributors George Vizkelethy (SNL),
Shinobu Onoda (JAEA) Center Funding Split NA