CSE 243: Introduction to Computer Architecture and HardwareSoftware Interface

1
CSE 243 Introduction to Computer Architecture
and Hardware/Software Interface
2
ARM Instruction Set Architecture

• Register structure
• Memory access
• Addressing modes
• Instructions
• Assembly language
• Subroutines
• Simple programs in ARM assembly language

3
Register structure

• Sixteen 32-bit registers labeled R0 through R15
• 15 general purpose registers (R0 through R14)
• Program Counter (PC) register R15.
• General purpose registers can hold data operands
  or memory addresses.
• Current program status register (CPSR) or Status
  Register
• Condition code flags (N, Z, C, V),
• Interrupt disable flags.
• Processor mode bits.
• 15 additional general purpose registers called
  banked registers.
• Duplicates of some of the R0 through R14.
• Used when the processor switches into the
  Supervisor mode or Interrupt modes of operation.

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Register structure (contd..)
31
0
R0
R1
15
General
purpose
registers
R14
31
0
Program counter
R15 (PC)
31
29
7
0
28
30
6
4
Status
CPSR
register
N - Negative
Z - Zero
Processor mode bits
C - Carry
Interrupt disable bits
V- Overflow
Condition code flags
5
Memory access

• Memory is byte-addressable, using 32-bit
  addresses.
• Two operand lengths are used in moving data
  between the memory and processor registers
• Bytes (8-bits) and Word (32-bits).
• Word addresses must be aligned
• Multiples of 4.
• Little-endian and big-endian addressing schemes
  are supported.
• Determined by an external input control line.
• When the length of the operand in a data transfer
  operation is a byte, the byte is stored in the
  low-order byte position of the register.

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Addressing modes

• Memory is addressed by generating the Effective
  Address (EA) of the operand by adding a signed
  offset to the contents of a base register Rn.
• Pre-indexed mode
• EA is the sum of the contents of the base
  register Rn and an offset value.
• Pre-indexed with writeback
• EA is generated the same way as pre-indexed mode.
• EA is written back into Rn.
• Post-indexed mode
• EA is the contents of Rn.
• Offset is then added to this address and the
  result is written back to Rn.

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Addressing modes (contd..)

• Relative addressing mode
• Program Counter (PC) is used as a base register.
• Pre-indexed addressing mode with immediate offset
• No absolute addressing mode available in the ARM
  processor.
• Offset is specified as
• Immediate value in the instruction itself.
• Contents of a register specified in the
  instruction.

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Instructions
ARM architecture is a RISC architecture Each
instruction is encoded into a 32-bit word.
Instruction format
31
28
27
20
19
16
15
12
11
4
3
0
Condition
OP code
R
n
R
d
Other info
R
m
Instruction specifies a - Conditional
execution code. - OP Code. - Two or three
registers (Rn, Rd, and Rm) - Other
information. - If Rm is not needed, other
information field extends to the last bit.
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Instructions (contd..)

• All instructions are conditionally executed,
  depending on a condition specified in the
  condition code of the instruction.
• Instruction is executed only if the current state
  of the processor condition code flags satisfies
  the condition specified in the high-order 4 bits
  of the instruction.
• One of the condition codes is used to indicate
  that an instruction is always executed.

10
Instructions (contd..)
Memory access instructions

• Memory is accessed using LOAD and STORE
  instructions.
• Mnemonic for LOAD is LDR and STORE is STR.
• If a byte operand is desired, then mnemonics are
  LDRB and STRB
• Recall that the memory is accessed by generating
  the effective address
• (EA) of the operand using various addressing
  modes.

Pre-indexed addressing mode (1) - Offset
specified as an immediate value - LDR Rd,
Rn,offset Pre-indexed addressing mode(2)
- Offset magnitude is specified in a register.
- LDR Rd, Rn,Rm - Contents of Rm
specify the magnitude of the offset. - Rm is
preceded by a minus sign if negative offset is
desired.
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Instructions (contd..)
Memory access instructions Pre-indexed addressing
mode with offset magnitude in a register.
1000
LDR R3, R5, R6
R5
Base register



200
R6
1000
Offset register


200 offset




Operand
1200
EA 1000 200 1200
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Instructions (contd..)
Memory access instructions
Pre-indexed with writeback (1) - Offset is
specified as an immediate value. - LDR Rd,
Rn,offset! - Exclamation mark indicates
writeback, that is the effective address
should be written back in Rn. Pre-indexed with
writeback (2) - Offset magnitude is
specified in a register. - LDR Rd, Rn,
Rm! - Exclamation mark indicates writeback,
that is the effective address should be
written back in Rn.
Pre-index with writeback is a generalization of
Autodecrement addressing mode.
13
Instructions (contd..)
Memory access instructions Pre-indexed mode with
writeback. Offset magnitude is specified in a
register.
1000
LDR R3, R5, R6!
R5
Base register



200
R6
1000
Offset register


200 offset




Operand
1200
EA 1000 200 1200 R5 1200
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Instructions (contd..)
Memory access instructions
Post-indexed (1) - Offset is specified as
an immediate value. - LDR Rd, Rn,offset
- Offset is added to Rn after the operand is
accessed and the contents are stored in
Rn. Post-indexed (2) - Offset magnitude
is specified in a register. - LDR
Rd,RnRm - Offset is added to Rn after the
operand is accessed and the contents are
stored in Rn.
Post-indexed addressing mode always involves
writeback. It is a generalization of
Autoincrement addressing mode.
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Instructions (contd..)
Memory access instructions Post-indexed
addressing. Offset magnitude is specified in a
register.
1000
LDR R3, R5 R6
R5
Base register



200
R6
1000
Offset register


200 offset




Operand
1200
EA 1000 R5 1000 200 1200
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Instructions (contd..)
Memory access instructions

• When the offset is given in a register, it may be
  scaled by a power of 2
• by shifting to the right or left.
• All the addressing modes, pre-indexed,
  pre-indexed with writeback and
• post-indexed.

• LDR R0,R1,-R2,LSL4!

Relative mode - Only the address of a
memory location is specified. - LDR R1,
ITEM. - This would normally be Absolute
addressing mode, but since there is no
absolute addressing mode, the EA is computed as
the offset of this memory location from
the PC. - Operand must be within 4095
bytes relative to the updated PC. (PC
points to the location following the instruction)
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Instructions (contd..)
Memory access instructions Relative mode
Memory
word (4 bytes)
address
1000
LDR R1, ITEM
1004
-
updated PC 1008
1008
-


52 offset




Operand
ITEM 1060
PC points to the word after the instruction
location. EA 1008 52
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Instructions (contd..)
Memory access instructions Block transfer
instructions

• Instructions for loading and storing multiple
  operands.
• Any subset of the general purpose registers can
  be loaded/stored.
• Mnemonic for Load Multiple is LDM, Store Multiple
  is STM.
• Memory operands must be available in successive
  locations.
• All forms of pre- and post-indexing with and
  without writeback can
• be used.
• Operate on a base register Rn specified in an
  instruction.
• Only word size operands are allowed.
• Useful in implementing subroutines, when multiple
  registers need to
• be stored onto the stack.

LDM R10 R0,R1,R6,R7 R10 is the base register
and contains 1000. Transfers the contents of
locations 1000, 1004, 1008 and 1012 to registers
R0, R1, R6 and R7 respectively.
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Instructions (contd..)
Register move instructions
Copy the contents of register R0 to register R1.
- MOV R1, R0 Load the an immediate operand in
the low-order 8 bits of register R0. - MOV
R1, 76
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Instructions (contd..)
Arithmetic instructions

• Arithmetic instructions operate on operands given
  in the general-purpose
• registers or on immediate operands.
• Memory operands are not allowed for these
  instructions (Typical of RISC
• architectures).

OPcode Rd, Rn, Rm - Operation is performed
using the operands in registers Rn, Rm. -
Result is stored in register Rd. OPcode Rd, Rn,
Operand. - Second operand may also be given
in an immediate mode. OPcode Rd, Rn, Rm, LSL 2
- When the second operand is specified in a
register, it may also be shifted left or
right.
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Instructions (contd..)
Operand shift instructions
Shifting and rotation operations are performed as
separate instructions in most other processors In
case of ARM, shifting and rotation operations can
be incorporated into most instructions. -
Saves code space and may improve execution time
performance.
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Instructions (contd..)
Conditional branch instructions

• Contain a signed 2s complement offset that is
  added to the updated
• contents of the PC to generate branch target
  address.
• Condition to be tested to determine whether or
  not branching should
• take place is specified in the high-order 4 bits
  of the instruction word.

31
28
27
24
23
0
1000
BEQ LOCATION
Condition
OP code
Offset
1004
Instruction format
updated PC 1008
LOCATION 1100
Branch target instruction
Note that in general the PC would have pointed to
1004. But here it points to 1008 for the reasons
of pipelined execution.
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Instructions (contd..)
Instructions to set condition codes

• Conditional branch instructions check the
  condition code flags in the
• status register.
• Condition code flags may be set by arithmetic and
  logic operations if
• explicitly specified to do so by a bit in the
  OP-code.
• Some instructions are provided for the sole
  purpose of setting condition
• code flags.

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Assembly language

• AREA indicates the beginning of a block of memory
• Uses the argument CODE or DATA.
• AREA CODE indicates the beginning of a code
  block.
• AREA DATA indicates the beginning of a data
  block.
• ENTRY directive indicates that the program is to
  begin execution at the following instruction.
• DCD directive is used to label and initialize a
  data operand.
• EQU directive is used to equate symbolic names to
  constants.
• RN directive is used to assign a symbolic name to
  a register indicative of its usage in the program.

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Subroutines

• Branch and link (BL) instruction is used to call
  a subroutine.
• Operates in the same way as other branch
  instructions.
• In addition, stores the return address of the
  next instruction following
• the BL instruction into register R14.
• R14 acts as a link register.
• For nested subroutines, the contents of the link
  register may be stored on
• the stack by the subroutine.
• Register R13 acts as the stack pointer.
• Parameters can be passed through registers or on
  the stack.

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Simple programs in ARM assembly language
Add N numbers - The first number is stored
at the starting address NUM1. - The count
of numbers to be added is stored at address N.
- Store the result at location SUM. -
Size of each number to be added is Word.
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Simple programs in ARM assembly language
Memory
Addressing
address
or
data
lab
el
Operation
information
Beginning of the code block
Assembler
directives
AREA
CODE
ENTR
Y
Begin execution from next instruction.
Statements
that
LDR
R1,N
generate
LDR
R2,POINTER
mac
hine
MO
V
R0,0
instructions
LOOP
LDR
R3,R2,4
ADD
R0,R0,R3
SUBS
R1,R1,1
BGT
LOOP
STR
R0,SUM
Beginning of the data block
Assembler
directives
AREA
D
A
T
A
SUM
DCD
0
Label initialize data operands
N
DCD
5
POINTER
DCD
NUM1
?
?
NUM1
DCD
3,
17,27,
12,322
END