CS3220: Processor Design

1
CS3220 Processor Design

• Spring 2005
• Jan 11 Lecture 0
• Prof. Gabriel Loh
• Today Administrivia, Semiconductors,
  Transistors, CMOS

2
Administrivia

• Textbook (mostly for reference)
• Patterson and Hennessey, Computer Architecture,
  The Hardware/Software Interface, 3rd Ed.
• Course where/when
• CCB 102
• TTh 430-600 (5 minutes as usual)
• Office Hours
• CCB 221
• TTh 600 700 (after lectures)
• Internet
• Course Webpage http//...
• My email loh_at_cc.gatech.edu
• Course IM gt 2005a cs3220 (AOL)

3
Overview

• Processor Design
• Pretty vague
• Past focuses
• Validation, Verification
• FPGA implementations
• Current focus
• Simulation-based methodology
• Main project
• Roll your own simulator

4
Grading

• Homework 15
• Three written problem sets, all in early part of
  course
• Projects 50
• Two small projects 10 each
• One large project for remaining 30
• Exams 35
• Midterm 10 (Feb 24)
• Quiz 5 (Apr 5) just to make sure youre
  keeping up
• Final 20 during finals weeks

5
Timing

• Last drop date is March 4th (Friday)
• Mid-term is on Feb 24 (Thursday)
• Mid-term grade, and grades for the 3 problem sets
  will be available before the drop date

6
Topics Outline (1)

• 1st five weeks
• Fundamentals
• Overview of semiconductors, transistors, gates
• Processor-centric logic design
• logic design review
• hardware algorithms for addition, multiplication,
  division, floating point
• FSMs for implementing processor control logic

7
Topics Outline (2)

• Next four weeks
• ISA Design
• RISC v. CISC, formats, modes, examples
• Pipelining Galore
• Data-paths, Control-paths
• Hazards, hazards, hazards
• Scoreboarding

8
Topics Outline (3)

• Next two weeks
• Caches
• Logic design of caches
• Cache design and tradeoffs
• Branch Prediction
• Stalls v. Delay Slots v. Prediction
• Static prediction
• Dynamic prediction
• Spring break is in the middle of this

9
Topics Outline (4)

• Last four weeks
• Advanced Topics/Potpourri
• Superscalar pipelines
• Techniques for high-frequency
• Power, Cooling, Battery Life
• Preview of follow-on courses

10
Pure/Intrinsic Silicon

• Regular crystal
• Each of the four valence electrons forms covalent
  bonds with neighboring Si atoms
• Very few free electrons
• Free charge carriers needed to conduct current
• Some are available due to thermal agitation

11
Charge Movement
Free Electron




Si
Si
Si
Si
















Si
Si
Si
Si









Free Hole








Si
Si
Si
Si












12
Hole Movement




Si
Si
Si
Si
















Si
Si
Si
Si















Carrier Mobility for holes is about 2x
slower than electrons





Si
Si
Si
Si













13
Doped Silicon (n-type)





P
Si
Si
Si

















P
Si
Si
Si




















P
Si
Si
Si













14
Doped Silicon (p-type)




B
Si
Si
Si
















B
Si
Si
Si


















B
Si
Si
Si













15
Conductivity

• Intrinisic Si is between conductor (metal) and
  insulator (e.g. glass)
• Hence Semiconductor
• Very dependent on temperature
• Higher concentration of dopants gives
• More charge carriers (either e- or holes)
• Greater conductivity

16
NMOS Transistor
W Transistor Width
L Channel Length (130nm, 90nm)
Source
Gate
Drain
Metal
Oxide (SiO2)
Metal
Metal
p-type Substrate
n
n
Body
17
NMOS Vgate 0
Source
Gate
Drain
Metal
Oxide (SiO2)
Metal
Metal
p-type Substrate
n
n
1012 W
Body
18
NMOS Vgate gt 0

Gate
Source
Drain

Metal
Oxide (SiO2)
Metal
Metal

p-type Substrate
n
n
Body
19
Threshold Voltage

• As Vgate increases, the channel area gets more
  depleted (no charge carriers)
• At the threshold voltage (VT), a channel is
  formed (the inversion layer) that allows
  conduction
• VT depends on
• Doping concentrations
• Substrate voltage (body bias)
• Temperature
• Other factors

20
NMOS Vgate gt 0, Vds gt 0


Gate
Source
Drain

Metal
Oxide (SiO2)
Metal
Metal
p-type Substrate
n
n
- - - - - - - - - - - - - - -
Body
21
NMOS Vgate gt 0, Vds 0


Gate
Source
Drain
Metal
Oxide (SiO2)
Metal
Metal
p-type Substrate
n
n
For a large Vds ( Vgs VT), the voltage
difference between gate and drain is smaller,
which results in a weaker electric field, which
attracts fewer electrons/ repels fewer holes,
thus resulting in a pinched channel, which
increases channel resistance.
Body
22
PMOS Transistor
Drain
Gate
Source
Metal
Oxide (SiO2)
Metal
Metal
n-type Substrate
p
p
Body

• Same as NMOS, but everything works in reverse
• Doping is reversed (p ? n)
• Body, Gate set to Vdd in off state
• Lower Vgate to make channel conductive
• Induced channel is p-type, carriers are holes

23
MOS Transistor Types
NMOS
PMOS
Symbol
VGate lt Vt
VGate gt Vt
24
CMOS

• Complementary MOS Circuits

Vdd
P pullup
x
f(x)
N pulldown
25
Ex CMOS Inverter

• If input 0, output 1
• If input 1, output 0

Vdd
Vdd
26
CMOS Implementation
Source
Gate
Drain
Drain
Gate
Source
Thick SiO2 (isolation)
SiO2
SiO2
Metal
Metal
Oxide (SiO2)
Metal
Metal
Oxide (SiO2)
Metal
Metal
n-type body
p
p
p well
n
n
27
Inverter Implementation
X

X
Thick SiO2 (isolation)
SiO2
SiO2
Metal
Metal
Oxide (SiO2)
Metal
Metal
Oxide (SiO2)
Metal
Metal
n-type body
p
p
p well
n
n
28
Ex NAND Gate
Vdd
Vdd
X
Y
out

• AND is 1 iff both inputs are 1
• NAND is 0 iff both inputs are 1
• Both X and Y must be 1 to open a path to ground
  (0)
• If either X or Y is 0, then one of the PMOS
  transistors provides a path to Vdd (1)

X
Y
29
Ex NOR Gate
Vdd
X

• OR is 0 iff both inputs are 0
• NOR is 1 iff both inputs are 0
• If either X or Y is 1, then one of the NMOS
  transistors provides a path to ground (0)
• Both X and Y must be 0 to open a path to Vdd (1)

Y
X
Y
30
Larger Example
Complement for PMOS (AB) . (CD) . (A(B.D)) .
(B((DA).C))
f(A,B,C,D) A.B C.D A.(BD) B.(D.AC)
A
B
31
Ex XOR

• f(X,Y) X.Y X.Y
• What to do about inverted variables?
• Make them inputs, too
• f(X,Y,X,Y) X.Y X.Y

X
Vdd
Y
f(X,Y,X,Y)
Vdd
Vdd
X
Y
X
Y
32
Ex XOR
Vdd
Vdd
X
Y
X
X Y
X
Y
Y