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failure analysis

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X-sectioning a CPGA package with. ULTRASLICE 6000 ... Xylem TM. 4. Substrate Thinning. Medium fine Diamond. 3. Cu Paddle. Milling Tool. 2. Package Removal ... – PowerPoint PPT presentation

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Title: failure analysis


1
failure analysis
enabling
  • an overview of

FA Sample Preparation
2
Selected Area Preparation
Silicon Thinning on ASAP-1
3
(No Transcript)
4
KEY PRODUCT AREAS
?
  • Precision Sawing
  • Precision Lapping and Polishing
  • Deprocessing
  • Cross-section Preparation
  • Consumable Products
  • Selected Area Preparation
  • Backside Analysis
  • Mechanical Decapsulation

?
?
?
5
ULTRA TEC Precision Sawing
ULTRASLICE 6000 Precision Saw
ULTRATRIM Diamond Trim Saw
6
Production ofPHYSICAL CROSS-SECTIONS
SEMI-AUTOMATIC X-sectioning a CPGA package with
ULTRASLICE 6000
MANUAL X-sectioning a BGA package with ULTRATRIM
7
Analyzing Physical Cross-sections
ULTRA TECs Measuring Microscope allows for the
determination of package layer thicknesses --
allowing for selected area and other preparation
protocols to be created.
8
Lapping Polishing
MULTIPOL TRUE FLAT LAPPING MACHINE
9
Ensuring Parallel Polishing
NEW TECHNOLOGY!
1 micronAccuracy Precision Micromount
Sub-micron Accuracy ULTRACOLLIMATOR
10
Selected AreaPreparationfor. Backside
Analysis Decapsulation
11
ASAP-1Selected Area Preparation System
MARKET LEADING SOLUTION
12
How thin do we need to thin ?
  • 100 microns remaining silicon usually thin enough
    for heavily-doped substrates
  • 50 to 80 microns ensures effective imaging
  • On lightly-doped substrates, 250 microns can be
    okay

Machinery discussed here can routinely Thin to lt
25 microns thickness
13
Using the Silicon Filter
  • Light Transmission

Microns of remaining silicon
14
Objective of Backside Selected Area Preparation
  • Remove package materials -- when die is
    encapsulated
  • Mechanically Thin substrate (die) to a known
    remaining thickness
  • Polish the surface to allow backside analysis

15
Schematic of backside preparation
1. PACKAGE to be prepared
2. A series of ASAP-1 tools is used to remove
package and substrate material and polish
3. The circuit is biased and package analyzed on
a backside microscope with I-R illumination
16
TEMP. RISE DURING PROCESS
Note Dry Grinding is not recommended. Dry grind
figures are to illustrate the difference in
thermal energy introduced by both Milling
(deterministic) and ASAP-1 (reactive) approaches
17
DETERMINISITIC vs REACTIVE
High Damage
Low Damage
Incremental Positive Steps
Gradual Wearing Away
Preset positive stop
Target
Target
REACTIVE ACTION e.g. ASAP-1
DETERMINISTIC ACTION e.g. Chip Unzip
18
Backside Prep - Process Steps
19
Which Size of Tool to use ?
The above sizes are standard. Other sizes are
available on request.
20
Easy Amplitude Set (Die or Cavity Size)
Read-out
Set Amplitude ½ Die Size ½ Tool Ø
Allowance
21
Testing Image Quality
Remaining Silicon Thickness ? F n t ? F is
the difference in focus from polished surface to
circuit n is the r.i. Of Silicon (approx 3.66) t
is the silicon thickness
INFRATEC-1 Backside Microscope
22
NIR Imaging Quality
Image taken with 2x objective on Alpha Innotech
FALCON PEM Note The background to this
presentation is the same part viewed with 100x
objective
23
Adjusting for Die tilt
Die
X
Y
Copper Remnant
Simple tilt accommodation is made after the
tell-tale non-cleanup of copper paddle /
silver halide epoxy
24
Sample Applications
FLIP CHIP
CERAMICS
CPGA thinning and polishing topside has been
glob topped to allow for backside prep
large flip-chip device Die size 31mm square
25
Sample Applications
Very Small Devices Sub-mm tools can be used to
thin very small areas on MEMS And surface-mount
devices
POWER CHIP PQFP with extremely thick die
paddle, (approx 3mm thick) after polishing
26
Sample Applications - 8 Wafer
27
Sample Applications Extremely Thin Substrates
50x Magnification
1000x Magnification
28
Sample Applications - Decapsulation
29
(No Transcript)
30
Anti-reflective Coating (ARC) for
BACKSIDE ANALYSIS
31
ARC - lite
32
Features of ARC- lite
  • Improves contrast up to 60
  • Improves emission sensitivity up to 30
  • Coating times are fast ( 45 secs)
  • Coating done at room temperature
  • System is bench-top can be positioned alongside
    ASAP-1 and/or microscope
  • Low cost

33
Application of Imaging Fluid
First apply ARC-lite solvent to prepare surface
run cycle Then apply 2-3 drops of imaging fluid,
and start cycle If re-coat is required run
cleaning cycle first, then re-coat
34
Sample After AR Coating
35
Before and After ARC Example 1
20x objective before ARC
20x objective after ARC
Imaged with IC Diagnostics Videre System
36
Before and After ARC Example 2
5x objective before ARC
5x objective after ARC
Imaged with Hypervision V2 emission microscope
37
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