Seminar in ComputerAided Design of VLSI Hardware Summary

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Seminar in Computer-Aided Design of VLSI Hardware
Summary

• Amir Rahat

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What is left for you to do

• At the end of the seminar, all participants
  should submit a short written review of the
  papers presented in the seminar, and their main
  points
• Of the papers presented in the seminar, and their
  main points
• About 2 pages of Word document or equivalent
• Please send it electronically (will be posted in
  the seminar web page)
• Individual work
• Submit within 3 weeks by July 5
• Review the main goals of the Seminar, see if they
  were met
• Understand the state of the art in Computer-Aided
  Design
• Study useful techniques and learn how to apply
  them
• Practice self-learning, presentation and review
  skills

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How will your work be graded?

• Grade Structure
• 65 for paper presentation
• 20 for class participation
• 100 Class participation requires at least two
  cases of notable contribution to the discussion
  in class, with deductions for more than 2
  absences and for being very late to class.
• 20 for homework
• 5 teacher's discretion
• Grades over 100 will be rounded to 100.
• Students will receive a short written review of
  their accomplishments, explaining how their
  grades were determined
• There will be no final exam, but there is a final
  review to be submitted
• Examples
• If you only attend your own presentation and it
  is perfect, you get 65
• If you do no homework, you cannot exceed 90
• If you get a balanced 90 on ALL your tasks, you
  can get a 100

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What did we learn - Review

• The fabrication process requires design of the
  geometrical shapes that make up transistors
  connections
• The VLSI design flow works in stages, and each
  stage has to be verified
• Architecture
• RTL
• Circuit
• Layout (and Post-Layout Circuit verification)
• Most activities require CAD tools
• Simulators
• Formal verification (mostly equivalence checkers)
• Synthesis tools
• Analysis tools
• There is still a lot of work to be done the
  flow is difficult, and takes many people and a
  lot of time to go thru
• No pushbutton tapeout yet

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The development process
The Design process
implement,
Specify,
Check,
produce
-Volume Mfg.
Definition
1st Silicon

• Do it right the first time - iterations increase
  cost and effort
• Overall trend from ART to ENGINEERING DISCIPLINE
  
• Issues complexity, correctness, productivity

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The Simple Design Flow Fully Automated
Nike's Software Architecture and Infrastructure
Enabling Integrated Solutions for Gigahertz
Designs
High-Level Formal Verification of
Next- Generation Microprocessors
Formally Verifying IEEE Compliance of
Floating-Point Hardware
Coverage Directed Test Generation for Functional
Verification using Bayesian Networks
Coverage-Oriented Verification of Banias
Advanced Techniques for RTL Debugging
Verification Strategy for Integrating 3G
Baseband SoC
Verification
Tape out
Circuit Design Environment and Layout Planning
Improved Global Routing by Amplified Congestion
Estimation
Evaluating benefits of Globally Asynchronous
Locally Synchronous VLSI architecture
Slope propagation in static timing analysis
A Novel Geometric Algorithm for Fast
Wire-Optimized Floorplanning
Redo
(In this flow, all circuit verification is done
after Layout, and Extraction includes Layout
verification
Quantum-dot Cellular Automata Computing by
Polarized Systems
Redo
Constraint-Based Watermarking Techniques for
Design IP Protection