Automatic ProcessOriented Control Circuit Generation for Asynchronous HighLevel Synthesis

1
Automatic Process-Oriented Control Circuit
Generation for Asynchronous High-Level Synthesis

• Department of Information and Communications at
  K-JIST
• April 5th, 2000
• speaker Euiseok Kim

2
Contents

• Introduction
• Preliminaries
• Approaches to Control Circuit Generation
• Controller Generation for CDFG
• Timing Constrains
• Experimental Results
• Conclusion

3
1. Introduction

• Asynchronous system design style becomes
  popular.
• Existing CAD tools are restricted to synchronous
  system design.
• ACAD tools are restricted to logic synthesis.
• Unwieldy to conceive and design controllers
  manually.

In order to overcome above problems, automatic
process-oriented controller generation method
from CDFG is presented as a part of an AHLS.
4
2. Preliminaries
DFG-UNIT
Control Dataflow Graph
DFG-Unit 1
CDFG-Unit 2
while 0 1
COND Node
Child Block
if 0 1
DFG-Unit 3


DFG-Unit


endif
DFG-Unit
5
3. Approaches to Control Circuit Generation - I

• Centralized Controller
• - unsuitable to asynchronous
• system style
• - may suffer from loss of parallelism,
• difficult hazard-free synthesis
• and rapid area increase.
• Hardware Oriented Controller
• - decompose global controller
• according to
• hardware allocation
• - may cause the same problems
• as centralized controllers

6
3. Approaches to Control Circuit Generation - II

• Process-Oriented Controller
• - Process Controller
• - Process Sequencing Controller
• - Control Node Controller
• - Unit Sequencing Controller

7
3. Approaches to Control Circuit Generation - III
Example
DFG-Unit 1
CDFG-Unit 2
while 0 1
USC
COND. Node
PSC
CNC
PSC
Child Block
if 0 1
DFG-Unit 3
PC
PC
PC
PC
USC


DFG-Unit
PC
PC
PC
PC
CNC
PSC


endif
PC
PC
PC
DFG-Unit
8
4. Controller Generation for CDFG - I
Derivation of PC
MUX
MUX
ReqStart
ReqOP1
ReqOP2t
FU ALU, MUL..
D
ReqFU
Working Phase
AckFU
ReqWDR
AckWDR
MUX
AckStart
ReqOP1-
ReqOP1-
ReqFU-
ReqWDR-
D
Register
AckFU-
AckWDR-
ReqStart-
AckStart-
idling Phase
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4. Controller Generation for CDFG - II
Derivation of PSC - I
start
R2
R4
R1
R3
PC1
PC2


OP1
OP2
ALU1
ALU2
R3
R2
PC4
PC3


OP3
OP4
ALU2
ALU1
end
R2
R3
10
4. Controller Generation for CDFG - III
Derivation of PSC - II
start
Req
ReqPC1
AckPC1
AckPC2
ReqPC2
ReqPC3
ReqPC4
PC1
PC2
AckPC3
AckPC4
Ack
PC4
PC3
Req-
ReqPC2-
ReqPC1-
ReqPC4-
ReqPC3-
AckPC2-
AckPC1-
AckPC4-
AckPC3-
end
Ack-
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4. Controller Generation for CDFG - IV
CNC Controllers
Req
Ack
CNC
ReqCon
ReqBlk
AckCon
AckBlk
Conditional Node
Child Block
Flag
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4. Controller Generation for CDFG - V
Derivation of USC
Req
Start
DFG-Unit 1
ReqBlk1
AckBlk1
CDFG-Unit 2
while 0 1
Block1
ReqBlk2
AckBlk2
Block2
Child Block
if 0 1
ReqBlk3
DFG-Unit 3
AckBlk3


Ack
DFG-Unit
Block3

Req-
endif

ReqBlk2-
ReqBlk1-
ReqBlk3-
End
AckBlk2-
AckBlk1-
AckBlk3-
DFG-Unit
Ack-
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4. Controller Generation for CDFG - VI

• A given STG should satisfy the following four
  properties in order to be synthesized into a
  speed-independent circuit.
• Boundedness
• Consistency
• Output Semi-Modularity
• Complete State Coding Property

PC, PSC, CNC and USC, which are derived through
the suggested method, satisfy above four
properties inherently !!!
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5. Timing Constraints - I
For correct control, designer should satisfy
following three timing constraints 1. DFU ?
Maximum OP Fetch Delay FUs worst case delay
Destination Registers input
Muxs worst case delay 2. DReg ? Worst case
delay for Register writing delay 3. For two
consecutive processes, Pi and Pj using the same
hardware, the idling phase of Pi should not
overlap with the working phase of Pj.
Constraint due to bundled delay
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5. Timing Constraints - II
Delay Constraint 3 - I
ReqFU1
FU/REGISTER
D
1
ReqFU2
1
PSC
0
1
1
0
1
0
1
0
PC1
PC2
1
0
AckFU1
AckFU2
1
1
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5. Timing Constraints - III
Delay Constraint 3 - II
ReqFU1
FU/REGISTER
D
0
ReqFU2
0
PSC
0
1
1
0
1
1
0
1
0
1
PC1
PC2
0
1
AckFU1
AckFU2
1
1
1
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6. Experimental Results - I
1
3
5



Adder1
Adder1
Adder1
Adder 1 Multiplier 1 Register 2
R1
R2
R1
2
4
6

MUL1
MUL1
MUL1
R2
R1
R2
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6. Experimental Results - II
Table 1. Controller Comparison between
Hardware-Oriented/ Process-Oriented methods
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6. Experimental Results - III
Differential Equation Solver
Async97, K. Y. Yun et al.
1
8
2
6
9
1
7
3
8
3
10
5
9
10
4
7
2
5
4
6
20
6. Experimental Results - IV
Table 2. Controller Comparison between
Hardware-Oriented/ Process-Oriented methods for
Differential Equation Solver
Async97 3D, K. Y. Yun et al.
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6. Experimental Results - V
Simulation result I - Controllers
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6. Experimental Results - VI
Simulation result II - Datapath
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7. Conclusion

• In this paper, we suggest an automatic
  asynchronous controller generation method based
  on process-oriented method having the following
  noticeable features
• to present a systematic and hierarchical way
• to produce STGs satisfying four properties for
  SI-circuit synthesis
• to be efficient in the points of area and
  performance
• to be useful for controller generation of
  large initial specification

Consequently, process-oriented method can be used
as an alternative approach to asynchronous
controller generation.