A Quasi-Delay-Insensitive Method to Overcome Transistor Variation

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A Quasi-Delay-Insensitive Method to Overcome
Transistor Variation

• Charlie Brej
• APT Group
• University of Manchester

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Overview

• Synchronous Problems
• Asynchronous Logic
• Why?
• How?
• Asynchronous Benefits
• Delay Insensitivity
• Early Output

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Problems Communication

• Communication horizon
• For a 60 nanometer process a signal can reach
  only 5 of the dies length in a clock cycle D.
  Matzke,1997
• Clock distributed using wave pipelining

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Cant keep ramping up the clock

• Intel pulls the plug on 4GHz Pentium 4
• AMD and Intel using PR based model numbers
• New ranges run at much slower clock rate
• Higher concentration on parallel execution
• Hyper-threading
• Multiple cores

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Problems Performance
Unbalanced Stages
Clock overheads
Clock Skew/Jitter
Transistor Variability
Timing Assumption overheads
Signal Integrity
Cycle time
Worst Average case performance
Real Computation
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Clock! What is it good for?

• No arguing with the clock
• 9am - 5pm. No excuses!

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Bundled-Data
Request Delay
Acknowledge

• When you finish, do the next task
• Flexitime

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Remove the Clock
Unbalanced Stages
Clock overheads
Clock Skew/Jitter
Transistor Variability
Timing Assumption overheads
Signal Integrity
Worst Average case performance
Cycle time
Real Computation
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How do you know when you are finished?

• Synchronous
• Estimate
• Global timing reference
• Asynchronous (bundled-data)
• Estimate
• Local delay elements
• Asynchronous (delay-insensitive)
• When the data arrives
• Intrinsic

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Becoming Delay Insensitive

• Dual-Rail
• Two wires
• 00 NULL
• 01 Zero
• 10 One
• (11 Not used)
• Four Phase handshake
• Return to zero

R0
R1
Ack
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Delay Insensitivity

• No assumptions on speed of wires or gates
• Environmental effects
• Heat
• Voltage supply
• Manufacturing defects
• Thin Film Transistor
• Next generation process sizes

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Early Output Logic

• Dual-Rail interfaces
• Output generated as early as possible
• Two Early output cases
• If either input is 0 then the output is 0

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Bit level pipelining

• Forward completed parts of the result
• Pace work
• Dont stall parts unless you have to

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Bit level pipelining

• Forward completed parts of the result
• Pace work
• Dont stall parts unless you have to

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Early Output cases
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Paper contribution

• With missing inputs still generates results
• Isolates late inputs
• Allows next data phase

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Remove Unnecessary computation
Unbalanced Stages
Clock overheads
Clock Skew/Jitter
Transistor Variability
Timing Assumption overheads
Signal Integrity
Worst Average case performance
Unnecessary Computation/Delays
Real Computation
Cycle time
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Summary

• Asynchronous
• Delay Insensitive
• Safe
• No timing assumptions
• Average case performance
• Remove unnecessary computation