RC6 Encryption Decryption Device

1
RC-6 Encryption/Decryption Device

• Carrie Yu
• Keith Jia
• Jonathan Discar
• ECE 111 Advanced Digital Designs
• March 3, 2005

2
Quick Overview

• Built an RC-6 Encryptor,
• Decryptor, and a key set
• VHDL was used to implement our
• design.
• We used a Spartan3 xcs4000
• chip for synthesis

3
Cryptography

• Overview

E(k)
D(k)
Bad Guy
Key Set K
Key Set K
4
RC6 Overview

• Advantages
• Fast
• Based on RC5 secure
• Disadvantages
• Requires 32-bit variables on rotations
• Integer multiplications on rotations
• 20 rounds
• Not Universally Practical

5
Importance of Different Keys

• Loss of Partial Information
• Someone who listens can repeat your encryption
  (duplication)
• Brute Attack more effective
• In order to prevent the above, we tried to
  implement a key set system for added security

6
Changes from Original Presentation

• Instead of creating separate encryption,
  decryption, and keyset chip, we only synthesized
  an encryption and decryption chip (each including
  a key set).
• No other changes

7
Encryption Block Diagram

• .

M
8
Decryption Block Diagram

• .

M
C
9
Looping Block Diagram - 1
10
Looping Block Diagram - 2
11
Looping Block Diagram - 3
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Looping VHDL

• begin
• Gate1 algo1 port map (Algo1_In gt Loopy_InB,
  Algo1_Out gt wire1)
• Gate2 algo1 port map (Algo1_In gt Loopy_InD,
  Algo1_Out gt wire2)
• Gate3 algo2 port map (Algo2_In gt Loopy_InA,
  Algo2_V1 gt wire1,
• Algo2_V2 gt wire2, Algo2_Key gt Loopy_Key1,
  Algo2_Out gt wire3)
• Gate4 algo2 port map (Algo2_In gt Loopy_InC,
  Algo2_V1 gt wire2,
• Algo2_V2 gt wire1, Algo2_Key gt Loopy_Key2,
  Algo2_Out gt wire4)
• Gate5 trade port map (Trade_In1 gt wire3,
  Trade_In2 gt Loopy_InB,
• Trade_In3 gt wire4, Trade_In4 gt Loopy_InD,
  Trade_Out1 gt Loopy_OutA, Trade_Out2 gt
  Loopy_OutB, Trade_Out3 gt Loopy_OutC,
• Trade_Out4 gt Loopy_OutD)
• end Structural

13
Key Set Block Diagram
Clk Reset Input
Event Handler
Counter
S0
S43
.
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Key Set VHDL

• begin
• process(input, clk)
• begin
• if( input'EVENT and clk'event and clk'1' )
  then
• output lt "1"
• else
• output lt "0"
• end if
• end process
• process( c_in, c_clk, c_reset, c_current )
• begin
• if( c_reset'1' ) then
• c_out lt "00"
• elsif( c_clk'event and c_clk'0' and c_in"1"
  ) then
• if( c_current"11") then
• c_out lt "00"
• else
• c_out lt c_current1

15
Toughest Part of VHDL Code

• Arbitrary Rotator Algorithm
• shft32 process(left, input, shift)
• variable shft integer
• variable out_right_arithmetic
  std_logic_vector(31 downto 0)
• variable out_right_logical
  std_logic_vector(31 downto 0)
• variable out_left_logical
  std_logic_vector(31 downto 0)
• begin
• shft to_integer(shift)
• shft shft mod 32
• if left '1' then
• out_left_logical input(31-shft
  downto 0)
• input(31 downto
  32-shft)
• output lt out_left_logical after
  250 ps
• else
• out_right_logical input(shft-1
  downto 0)
• input(31 downto
  shft)
• output lt out_right_logical after
  250 ps
• end if
• end process shft32

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Toughest Part of VHDL

• To Integer
• function to_integer(sig std_logic_vector)
  return integer is
• variable num integer 0 -- descending
  sig as integer
• begin
• for i in sig'range loop
• if sig(i)'1' then
• num num21 --mult digit by 2
  then 1 if 1, else mult by 2
• else
• num num2
• end if
• end loop -- i
• return num
• end function to_integer

17
Demonstration 1 Waveform
18
Demonstration 1 Waveform
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Demonstration 1 Waveform
20
Demonstration 1 Waveform
21
Demonstration
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Demonstration 2 Explanation

• First, we sent our username, ckj
  00000000000000000000000000636B6A
• Second, our password love 000000000000000000000
  0006C6F7665
• Wrong Password, try again. Resend ckj
  00000000000000000000000000636B6A
• Finally, send our real password, secret
  000000000000000000000736563726574

23
Demonstration 2 Explanation

• First ckj encrypted to 39C605340DC54CE35073442F
  11B41E74
• love encrypted to
• 62E65CE7C66BB450BFB900BCCA498062
• Second ckj encrypted to
• 99093AE3A9D0EC1E6C3A48445C5B2A01
• secret encrypted to
• 288FE8A3590E6612B611EF2AFE2B06F9
• We fed these ciphertexts into the decryptor and
  got our original messages back.

24
Synthesis

• We used Spartan3 xcs4000. Large chip because of
  added keyset and amount of calculations.
• Amount of time to get our computers back from
  the dead bout an hour
• Note Max IOB is only 633

25
Our Key Component
26
Single Loop Component
27
The Circuit Overview
28
Encryptor Place and Route
29
Decryptor Place and Route
30
HDL Synthesis Report

• Macro Statistics (same for both)
• Multipliers 30
• Adders/Subtractors 35
• Multiplexers 1860
• Xors 30

31
Synthesis Summary
32
Difficulties

• Arbitrary rotating code was a bit tricky
• Implementing the key set was also tricky
• Synthesis due to length and limitations.

33
Looking Back

• 1) Implemented a more sophisticated key
  synchronization algorithm to increase security.
• 2) Spend more time optimizing the circuit. We
  focused on security rather than speed and area.
• 3) Perhaps breaking the chips up
• even further to meet our original
• goals.

34
Summary

• Whatve we learned?
• 1) Division of labor
• 2) Reverse engineering
• 3) Code reuse ex rotater
• 4) Synchronization is painful and long.
• 5) RC6 is a good encryption algorithm. It
  relies
• on a lot of computations.

35
Thanks, and heres a random comic
36
Keys and locks

• This lock is pretty

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