SPEEDES Trifold

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SPEEDES
For many simulation objects, their state changes
at a much lower frequency than the frequency of
events that make use of the object.  SPEEDES uses
a scheme that reduces the message traffic between
CPUs by establishing object proxies at CPUs that
need access to those objects' states, and
requiring inter-CPU messages only when the proxy
state needs to be updated because of a change to
the object it represents. Also, object
subscribers may not need all the state data from
a particular object proxy.  SPEEDES uses an
optimization scheme whereby proxies can
dynamically subscribe either to entire objects,
or only to attributes that are of interest to
them. The release of SPEEDES version 2.2,
provides significant advances in parallel
discrete event simulation. This release is the
culmination of two years of enhancements and
lessons learned on the Ballistic Missile Defense
System Simulation (BMDS-SIM) project. SPEEDES
has supported real-time BMDS-SIM simulations on 1
through 48 processors. Version 2.2 enhancements
were funded under a variety of contracts
including both MDWAR and International Programs
(IP) at the Joint National Integration Center
(JNIC) and the Air Force Research Lab (AFRL) in
Rome NY. The work to test and release Version 2.2
was funded by Northrop Grumman Corporation.
SPEEDES allows each of an unlimited array of
processors to race ahead with an assigned set of
events, create messages, etc. without regard to
processing on other CPUs.  Then, anytime a
'straggler' message arrives at a CPU that
invalidates the processing that has been going on
at that CPU, the processing is rolled back and
any messages sent as a result of the invalid
processing are cancelled.  Other CPUs that
receive message cancellations then may be rolled
back, and so on.  The algorithms also allow the
user to balance 'at-risk' forward processing of
events that may have to be undone and
re-processed, with risk-free forward processing
of events whose output messages can be held until
needed by other events.
Synchronous Parallel Environment for Emulation
and Discrete-Event Simulation. The SPEEDES
simulation engine allows the simulation builder
to perform optimistic parallel processing on high
performance computers, networks of workstations,
or combinations of networked computers and HPC
platforms.  Applications that can make use of
SPEEDES are typically time-constrained (too many
events to process in a limited amount of time).
What are the benefits?   SPEEDES-based
object-oriented simulations that run on High
Performance Computing (HPC) platforms are able to
address extremely complex problems and still
maintain short run times.  Where 'real time'
simulation is required, as in wargames or
training, SPEEDES optimistic processing
capability minimizes simulation lag time behind
wall clock time, or multiples of real time.  
Likewise, when fast completion of a virtual time
simulation run is needed, SPEEDES accommodates
increases in problem complexity with additional
parallel computing nodes. How does SPEEDES
work?   SPEEDES allocates events over multiple
processors to get simulation speed-up.  This
characteristic improves runtime, especially when
exploiting the very large number of processors
and the high-speed internal communications found
in HPC platforms.  At the heart of SPEEDES is a
set of innovative optimistic-processing
algorithms.
Development and Use
Developed, maintained, and distributed
by METRON Metron supplies source code to
qualified (U.S. only) users at no charge On-line
documentation at www.speedes.com Primary
users JNIC Ballistic Missile Defense System
Simulation (BMDS-SIM) Air Force Research Lab
Force Structure Simulation (FSS)
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SPEEDES
SPEEDES Lead Developers
CSPEEDES
METRON has also completed a Northrop Grumman
funded project to rehost the U.S. Navy
SPAWAR-developed Common Component Simulation
Engine (CCSE) on SPEEDES version 2.2. The merged
product is called CSPEEDES. Metron demonstrated
that objects using the Federation Object (FO)
interface could interact simply with objects
using the Object Proxy interface used by BMDS-SIM.
Ron Van Iwaarden PhD, Applied Mathematics,
University of Colorado SPEEDES developer for 9
years SPEEDES design, development and
documentation JNIC MDWAR wargame support
Software Framework/toolbox for building parallel
C simulations Distributes simulation over
multiple CPUs Coordinates simulation activities
between CPUs
Gary Blank MS, Comp. Science, University of
Virginia BS, Applied Mathematics, Brown
University SPEEDES developer for 9 years DSF
design, development SPEEDES support of
AFRL SPEEDES enhancements HLA RTI developer
Dynamic Simulation Framework (DSF)
This major new parallel processing engine, based
on SPEEDES, allows users to emulate a realtime
process and at any time initialize multiple rapid
course-of-action simulations to support real-time
decision making. DSF engine development is being
funded by the Information Technology Division of
the Air Force Research Lab at Rome, NY.
Jacob Burckhardt BS, Computer Science, UC
Berkeley SPEEDES developer for 9 years SPEEDES
enhancements CCSE sim engine IVV SPEEDES
testing SPEEDES Configuration Mgt.
For more information contact James S
Brutocao Senior Software Analyst Metron, Inc. 512
Via de la Valle Suite 301 Solana Beach, CA
92075 Phone [phone] Fax (858)
792-2719 Email brutocaoj_at_ca.metsci.com Web
www.metsci.com www.speedes.com
Janie Wojdyla BS, Computer Science, Southwest
Texas State University Software developer for 14
years JNIC BMDS-SIM SPEEDES support
Applications of Mathematics, Operations
Research, and Simulation Sciences
Operations Analysis Simulation Sciences High
Performance Computing