Data Transfer Protocols : Motivation 1

1
Data Transfer Protocols Motivation - 1

• Need to develop some universal methodology to
  cater to wide varieties of Peripheral Memory
  devices.
• Keeping the flexibility of connecting any type of
  peripheral/ memory with any CPU.
• Reduces market monopoly and encourages companies
  to adopt to a common universal standard.

2
Data Transfer Protocols Motivation - 2

• All processes/programs must ask for any service
  from the system (CPU O.S.) in an uniform
  manner.
• Any process asking for any services/resources
  from the system (O.S. CPU) that includes
  peripheral operation can be provided that
  service/resource as soon as it becomes available
  in a Fair way ( normally done by the scheduler) .
• Any peripheral interface must be capable enough
  to proceed on its own i.e. the CPU as well as
  the concerned peripheral proceeds simultaneously
  with their tasks , CPU with a CPU bound process,
  peripheral with a peripheral bound job. This
  helps, in a large extent, to improve the
  utilization of the CPU.
• After / During availing of the requisite
  service(s) / peripheral , the concerned process /
  peripheral must be able to draw CPUs attention
  via some in built universal mechanism in order to
  satisfy criteria 2.

3
Various ways of classifying Peripherals - 1

• Classification A
• Input .
• Output .
• Memory.
• Classification B
• Storage Devices.
• Character Devices.
• Communication Devices.

4
Various ways of classifying Peripherals - 2

• Classification C
• Slow Inexpensive.
• Fast Expensive.
• Classification D
• Block oriented .
• Character Oriented.

5
Factors affecting Data Transfer protocol Design
involving CPU peripheral / Memory

• Connectivity between Sender Receiver (
  Serial / Parallel) .
• Varying Data Formats.
• Electrical characteristics of the peripheral
  interface.
• Relative Speeds ( Sender Receiver as well as
  the interconnecting lines / bus).

6
Classification of Data Transfer protocols as
employed between CPU Peripherals / Memory

• A. Relative Speeds of the Sender Receiver
• A1. Synchronous.
• A2. Asynchronous.
• B. Implementation Style / Technique .
• B1. Programmed.
• B2. Non Programmed.

7
Classification of Data Transfer protocols based
on Sender Receiver Speeds

• A1. Synchronous When the concerned
  peripheral / memory is either speed compatible
  with the CPU or CPU has got a-priori knowledge
  about its speed . ( Rare phenomenon).
• A2. Asynchronous When CPU is oblivious
  about the speed(s) of the concerned peripheral /
  memory. (Normal Phenomenon).

8
Classification of Data Transfer protocols based
on Implementation

• B1. Programmed When the data transfer
  (send/receive) between CPU peripheral is
  accomplished by executing some form of program /
  series of machine instructions I.e. involving the
  CPU.
• B2. Non Programmed When the data transfer
  takes place between CPU some peripheral OR CPU
  memory directly without executing any program .
  In this case data transfer to/from peripheral
  from/to memory does not involve the CPU.

9
Practical Usage of the various Data Transfer
Protocols

• Synchronous Non Programmed.
• Synchronous Programmed Higher Speed
• Asynchronous Low Speed .
• - Polling.( Non Programmed Programmed).
• - Interrupt ( Hardware Software
• Always Programmed ).
• Asynchronous Non- Programmed
• 
  Highest Speed
• - Direct Memory Access DMA.

10
Various types of Data Transfer

• Peripheral to CPU INPUT / (READ).
• CPU to PeripheralOUTPUT/ (WRITE) .
• CPU to Memory STORE / (WRITE).
• Memory to CPU LOAD / FETCH / (READ).

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Synchronous Data Transfer ( Programmed / Non
Programmed ) From CPU WRITE

• 1) CPU floats the address of the
  receiving peripheral / memory via address bus.
• 2) Next CPU pushes Data via its Data
  Bus as well as asserts write signal via control
  bus.
• 3) CPU waits for some pre fixed time
  before sending the next data either by waiting at
  the Control Unit /Firmware Level (Non
  Programmed) OR by repeatedly executing some
  special NOP ( No Operation) instruction (
  Programmed) in a loop.

12
Synchronous Data Transfer ( Programmed / Non
Programmed ) To CPU READ

• 1) CPU floats the address of the sending
  peripheral / memory via address bus as well as
  asserts READ signal via its control bus.
• 2) CPU waits for some pre fixed time
  either by waiting at the Control Unit /Firmware
  Level (Non Programmed) OR by repeatedly
  executing some special NOP ( No Operation)
  instruction ( Programmed) in a loop, before
  latching the valid read data from the system Data
  Bus.

13
Synchronous Non Programmed Data transfer, A
Special Case

• CPU ?gt Slow Electronic Memory Interface. since
  the CPU cannot have access to any stored program
  unless it can access its Memory but CPU is
  aware about the relative speed of the memory.
• CPU , in order to access the slow memory ,should
  wait for prefixed time at its control unit
  level before either probing Data Bus for valid
  Data or sending the next Data to the Data Bus.
• Some other Special Techniques like Interleaving,
  Look Through Cache, are adopted to reduce this
  CPU Waiting Time.

14
Asynchronous Data Transfer Operation

• The most widely used .
• Can be Programmed or Non Programmed.
• Three main types
• Polling. ( Programmed / Non Programmed) .
• Interrupt Driven ( Programmed Hardware /
  Software .
• Direct Memory Access ( DMA)
• Non Programmed .

15
Asynchronous Data transfer ( POLLING ) WRITE

• 1) CPU floats the address of the
  receiving peripheral /memory via address bus.
• 2) Next CPU pushes Data via its Data
  Bus as well as asserts write signal via control
  bus.
• 3) CPU waits / polls device readiness
  status by executing some loop (busy waiting)
  applicable only for peripheral for some pre
  specified data receipt/written acknowledgement
  signal from the receiving peripheral /memory
  before sending the next data.

16
Asynchronous Data transfer ( POLLING ) READ

• 1) CPU floats the address of the sending
  peripheral / memory via address bus as well as
  asserts READ signal via its control bus.
• 2) CPU waits / polls device readiness
  by executing some loop (busy waiting) applicable
  only for peripheral for some pre specified data
  ready signal from the sending peripheral before
  probing the data bus for valid data.

17
Asynchronous Data transfer ( POLLING ) Features

• Normally Programmed Polling is in use.
• Any process User Program may go into busy
  waiting loop waiting for an event to happen ,
  like receipt of some message, for a shared data
  structure to be free.
• The busy waiting loop structure
• WHILE (NOT Ready) DO No-Op / WAIT
• This consumes CPU time unnecessarily.

18
Various Types of Interrupt

• Most widely used in asynchronous Data Transfer.
• Following methodologies are available
• Software Interrupts used to
• a) Implement System Calls needed to
  signal the O.S. to initiate the Data Transfer.
• b) Notify the debugger about a specific
  event . Useful for handling certain errors.
• 2. Peripheral / Device / Hardware Interrupts
  ( Maskable / Non Maskable) used to resume a
  partially complete transfer / to handle the
  completion of the data transfer involving the
  concerned Device.
• Presence of both these facilities are a must to
  support the concept of Multiprogramming.
• 3. Various Exceptions FAULT (with correction
  resumption facility), TRAP (Debug with No
  resumption) ABORT.

19
Interrupting Peripherals ( Device / Hardware
Interrupts)

• Normal CPU Device Connectivity

ADDr Bus
Peri1
INTR
CPU
Interrupt Controller
Data Bus
IRQ 1
INTACK
PeriN
Data Bus
Data Bus
IRQ N
Data Bus
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Interrupt Handling Protocols

• Concerned Peripheral raises Interrupt Request
  (IRQ) Line.
• Each IRQ line can be selectively MASKED or
  disabled momentarily through Instructions.
• IRQ lines can be assigned prefixed priorities.
• Interrupt Handler for each Peripheral are already
  written in the form of Device Driver which are
  invoked via specific starting addresses (
  Interrupt Vectors) .
• On receiving any unmasked IRQ the Interrupt
  Controller converts it into the corresponding
  Interrupt Vector.
• Stores the Vector in an I/O port within the
  Controller so that CPU can read it via DATA Bus.
• Raises the INTR line of the CPU to ask for
  service.
• On completion of the current Instruction
  Execution, CPU will raise INTACK signaling start
  of the Interrupt Service.This will cause clearing
  of the corresponding raised IRQ.

21
Device Interrupt Handling Sequence

• Process Interrupt 1 CPU enters Kernel Mode
  from the User Mode after saving the current
  execution status return address in the System
  Stack.
• Process Interrupt 2 The CPU Sends Interrupt
  Acknowledgement Signal to the Interrupting Device
  and in this course also uniquely identifies the
  Interrupting device.
• Process Interrupt 3 After receiving the
  Interrupt Acknowledge Signal from the CPU , the
  actual / identified Interrupting Device provides
  the starting address of its Interrupt Service
  Routine (ISR) / the Interrupt Vector via the Data
  Bus to the CPU.
• After obtaining the ISRs starting address , the
  CPU jumps to it in order to service the
  interrupt.
• Inside the ISR, the CPU first disables all the
  Interrupts of the same type at the lower
  priority level, saves all the Registers Locals
  in the system stack, then proceeds with the
  Interrupt service.
• Interrupt Service Waking up the process that
  was busy with the peripheral activities as well
  as all other processes that were waiting for that
  peripheral usage and making all of them Ready to
  be scheduled next.
• At the end , CPU restores all status , enables
  all disabled interrupts and resumes the previous
  process at the point it was left.

22
Typical Peripheral Usage Sequence- 1

• Each user program asks for Peripheral Service
  from the underlying Operating System through
  dedicated System Call (Software Interrupt /
  Supervisor Call SVC) while executing.
• Any SVC causes the underlying user process to
  enter Supervisor / Kernel mode where it can
  access the complete report ire of the underlying
  CPUs Instruction Set.
• While in Supervisor Mode the O.S. starts
  executing and does the following
• Saves the concerned Processs context in the
  system Stack.
• Monitors the Status Register(s) of each of the
  different instances of the concerned peripherals
  to see whether any of it is free.
• If none of the instances are free then the
  requesting process is put in the WAIT state .
• If , however, any of the instance of the
  requested peripheral is indeed free then the O.S.
  allocates that instance of that peripheral in
  the manner illustrated later to the requesting
  user process and mark that instance as occupied.

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Peripheral Usage Sequence - 2

• 4. Execute Device Driver Program to perform
• a) Filling up of peripheral buffer(s)
  from designated memory if needed.
• b) Load the peripheral Interface
  command register to start operation.
• Mark the process State as WAIT.
• Another Process from the READY Queue is selected
  for execution by the O.S. and dispatched /
  scheduled to the CPU.
• On completion of the peripheral Operation, the
  concerned peripheral Interface issues an Hardware
  Interrupt.
• In response the O.S. while servicing that
  interrupt, mark that resource instance as free
  and also restore s the state of ALL the WAITING
  processes to READY.

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The Asynchronous Non Programmed Data Transfer
(The Direct Memory Access DMA )

• Used when Programmed Transfer will slow down the
  transfer rate since Programmed transfer ?
  executing a program to accomplish Data Transfer
  which involves fetching the instructions of the
  Program from Memory.
• Usually resorted when it takes time to locate
  the starting point of a reasonably large Data
  Block to be READ from a peripheral or alternately
  a large Memory Area whose content is to be
  transferred to the concerned Peripheral Interface
  ( Normally reading writing any Disc Media).
• Two ways 1) Cycle Stealing 2) Burst Mode.

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The Asynchronous Non Programmed Data Transfer
(The Direct Memory Access DMA ) Typical
Operation Sequence.

• User process asks for service / peripheral
  operation by an appropriate system call (
  Software Interrupt).
• CPU enters Kernel Mode from the User Mode after
  saving the current execution status return
  address in the System Stack.
• The CPU identifies the concerned device.
• Then the CPU loads the Starting Address of the
  Data Block in memory from / into where the data
  is to be written to / read from the Peripheral
  Interface. It also loads the word count / size of
  the data block to the DMA controller .
• The CPU initiates the DMA by sending appropriate
  command to the DMA Controller.

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The Asynchronous Non Programmed Data Transfer
(The Direct Memory Access DMA ) Typical
Operation Sequence.

• 5. After initiation, whenever the concerned
  device becomes ready to send/receive data , it
  requests the DMA Controller, . In response, the
  DMA controller sends the HOLD request to the CPU
  asking it to release all the bus ( Address, Data
  Control) l of the selected Memory Module for
  its exclusive usage.
• 6. In response , CPU may momentarily release
  the buses and send HOLDACK signal to the DMA
  controller . In this case , the DMA controller
  gets to transfer at lest one data word from /to
  memory to from the concerned DMA peripheral . The
  transfer takes place whenever CPU is not
  accessing the relevant memory ( say during
  Instruction Decoding or alternately whenever CPU
  is being catered to by the CACHE Memory) .
  Cycle Stealing.
• 7. Alternately CPU releases all the buses
  for a sufficient long period, to allow data
  transfer in burst mode from /to the concerned
  device to/from the selected memory module via the
  DMA Controller.
• 8. After each word transfer, the Word Counter
  gets decremented.
• 9. On completion ,i.e. Word Counter becoming
  0, the DMA controller sends an Hardware interrupt
  to the CPU which is handled as illustrated
  before.

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The Direct Memory Access DMA Typical Issues.

• The Peripheral Devices involved in DMA transfer
  are normally Block Oriented Devices.
• The Memory Block involved in the DMA data
  Transfer represents a Shared Memory between the
  CPU and the concerned peripheral.
• Unless the DATA Transfer to/from the Concerned
  Peripheral is complete that piece of Shared
  Memory must not be accessed by the CPU in order
  to maintain Data Coherency.
• No portion of the Memory Block involved in the
  DMA transfer should be resident in the previous
  hierarchical levels I.e.the Cache in order to
  maintain Data Coherency. Hence all Cached Copies
  of this Memory Block gets marked as INVALID.
• Any DMA operation too must be initiated by some
  Supervisor Call and terminated by some Hardware
  Interrupt to ensure O.S. Control.