ADF4193 Low Phase Noise, Fast Settling PLL Frequency Synthesizer

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ADF4193Low Phase Noise, Fast Settling PLL
Frequency Synthesizer
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BASED ONA 10ms Fast Switching PLL Synthesizer
for a GSM/EDGE Base-Station

• By
• Mike Keaveney, Patrick Walsh,
• Mike Tuthill, Colin Lyden, Bill Hunt

ISSCC 2004 / SESSION 10 / CELLULAR SYSTEMS AND
BUILDING BLOCKS / 10.6
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FUNCTIONAL BLOCK DIAGRAM
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No connection here
50O
52O
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FEATURES

• New fast settling fractional-N PLL architecture
• Single PLL replaces ping-pong synthesizers
• 0.5 degree RMS phase error at 2 GHz RF output
• Digitally programmable output phase
• RF input range up to 3.5 GHz
• 3-wire serial interface
• On-chip low noise differential amplifier
• Phase noise figure of merit 216 dBc/Hz
• Loop filter design possible using ADI SimPLL
• APPLICATIONS
• GSM/EDGE base stations
• PHS base stations
• Instrumentation and test equipment

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Background GSM Base-station Synthesizer
Requirements

• Switch frequency in 10ms gt Wide PLL BW
• Low Phase Noise during Data Burst
• Low Spurious during Data Burst

gt Narrow PLL BW
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Phase Noise Lock Time Simulations
N1880/104 0.875M/(2pN)528k
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8x Bandwidth Switching
64x ICP
1x ICP

Wide BW 64x ICP R/8 Narrow BW 1x ICP
R
Ref Crowley 78
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PLL Static Phase Error
Matched
Mismatched
Fref
Fdiv
UP
DOWN
t ? DICP
Dt ? ICP
ICP
Charge Balance
-ICP
Dt
t
At Balance Dt ? ICP t ? DICP 5º _at_
1.85GHz ? 7.5ps (? 0.065º _at_ 26MHz) With t
3ns, for Dt lt 7.5ps, requires ICP mismatch lt
0.25
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Conventional Charge Pump PLL
ICP Envelope
0
64x
1x
64x ? 1x ICP mismatch D 10 ? Df 200
Ideal
Time (5ms / div.)
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Differential Charge Pump Concept

• Better Up/Down Matching
• Same Type Devices
• Symmetric Layout
• Charge Injection is Common Mode to Vtune
• Requires
• Low Noise Diff-amp
• CMFB
• Matching improved but still residual mismatch due
  to process (? 0.5)

mp1
mp2
Vbias1
Vtune
DNp
UPp

CPO
CPO
UPn
DNn
Vbias2
mn1
mn2
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Charge Pump Cell with Chopped Outputs
5V
mp1
mp2
Vbias1
UPp1
DNp2
DNp1
UPp2
CPO
2V
CPOB
2V
DNn1
UPn2
UPn1
DNn2
Vbias2
mn1
mn2
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Chopped Up/Down Signal Paths from PFD
f1
Fref
UP1, DN2
D
Q
f2
RB
t
RB
f2
D
Q
Fdiv
DN1, UP2
f1
f1
f2
Fref
Fdiv
Chopped Output Charge
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Diff-Amp
CPO
Vout
1000?0.5
Vref
1000?0.5
500
500
CPO
5mA
5mA

• PLL suppresses DC errors 1/f noise.
• Want zero IIN mismatch ? MOS i/ps
• Noise gt 40kHz ? FM sidebands
• ? lt 7nV/?Hz required _at_ Vout

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Common Mode Feedback Loop

• Pulse Stretch circuit
• ? Fast leading edge, current controlled trailing
  edge
• ? Control current mirrored to both up and down
  pulses.

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CMFB Pulse Stretch Signals
from PFD
UP
DN
to PMOS switches
UPp
DNp
to NMOS switches
UPn
DNn
Phase info from PFD remains intact
Differential CP output
Common Mode output
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Proposed Fast Locking PLL
Open R2 R3 switches when ICP is _at_ 1x
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ICP Reduction with SD Compensation
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Measured Phase Lock Time
75 MHz jump from 1880 to 1805 MHz
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Chopping Off vs. Chopping On
Measured 1 ICP mismatch change ? 20 phase
step w/o chopping
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Measured Output Phase Noise
DCS-1800 Tx LO Mask
dBc/Hz
RMS Phase Error (SSB) 0.25
Fout 1860MHz, Fref 26MHz, Chopping _at_
Fref/2 External VCO (Vari-L 1843T)
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Measured Spur Side-Band Levels
Chopping _at_ Fref/2, (with 2 measured ICP mismatch)
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Die Photo
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Performance Summary
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Summary

• Static Phase Error due to Up to Down Mismatch in
  the PFD and Charge Pump blocks can be eliminated
  using a chopping scheme.
• Loop Gain Changes during BW switching can be
  digitally compensated for in the SD Modulator.
• A PLL based synthesizer can jump over the full TX
  band in lt10ms and still meet the phase noise and
  spurious requirements for a GSM and EDGE
  base-station.