Charge Pump PLL

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Charge Pump PLL
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Outline

• Charge Pump PLL
• Loop Component Modeling
• Loop Filter and Transfer Function
• Loop Filter Design
• Loop Calibration

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Charge Pump PLL

• The charge pump PLL is one of the most popular
  PLL structures since 1980s
• Featured with a digital phase detector and a
  charge pump
• Advantages
• Fast lock and tracking
• No false lock

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Phase Detector

• Gives the phase difference between the input
  clock signal and VCO output signal
• Different types
• Nonlinear (such as Bang-Bang)
• Linear (such as Hogges Phase Detector)
• Linear PD output a digital signal whose duty
  ratio is proportional to the phase difference
• In Hogges PD, if the phase difference is ?e ,
  the output digital signal duty ratio is

C. Hogge, A Self-correcting clock recovery
circuit, Dec, 1985
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Typical Phase Detector and Waveform
Circuit Structure
Output Waveform When locked
Y. Tang, et., al., "Phase detector for PLL-based
high-speed data recovery," Nov. 2002
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Charge Pump

• Convert a digital signal into current

UP
Iup
Idn
DN
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Loop Filter

• Low pass filter
• 1st order
• 2nd order (higher roll-off speed at high
  frequency)
• 3rd order higher

Ip
Ip
VC
VC
C1
C1
C2
R
R
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VCO

• Tuning gain KVCO is the most important parameter
• Usually coarse tuning and fine tuning

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CP PLL loop modeling
fi
fo
Phase Detector
Charge Pump
Loop Filter
VCO
fo
?i
?o
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2nd Loop Transfer Function

• Using a 1st order LPF Active PI type
• Open-loop transfer function
• Closed-loop transfer function

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3rd Loop Transfer Function

• Using a 2nd order LPF
• Let mC2/C1
• Open-loop transfer function
• Closed-loop transfer function

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Comparison

• When m becomes 0, the 3rd order loop degenerates
  into 2nd order loop
• 3rd order loop gives an extra high frequency
  pole, which increases the high frequency roll-off
  in jitter transfer
• 3rd order loop is widely used and can be treated
  as 2nd order loop for simplification
• Unfortunately, the 3rd order loop shows different
  jitter transfer from the 2nd order loop
• We focus on 3rd order loop

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Simplification of 3rd Order Loop

• Define natural frequency ?n damping ratio ?
• Then totally 3 loop parameters ?n, ? m
• Simplified transfer function

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LPF Design Consideration

• 3-dB frequency easy to control
• Roll-off speed easy to meet with 2nd and 3rd
  order transfer function
• Jitter transfer (jitter peaking)

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Jitter peaking of 2nd order loop

• Jitter peaking can be reduced or eliminated by
  increasing the damping ratio
• Eliminated when damping ratio ? gt1
• Large damping ratio leads to slow closed-loop
  response
• Usually suggested ?5 to meet the jitter peaking
  spec

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Jitter peaking of 3rd order loop

• Usually believed to be similar as the 2nd order
  loop
• Actually quite different from the 2nd order loop
  case
• Jitter peaking always exists even with very large
  ?
• Need to be treated carefully

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Jitter peaking is dependent on ? and m

• m0 (2nd loop)
• jitter peaking can be reduced or
  eliminated by using large ?
• mgt0 (3rd loop)
• ? is quite small, increasing ? will decrease the
  jitter peaking
• ? is larger than a threshold value ?m, increasing
  ? will increase the jitter peaking

Jitter peaking versus damping ratio and
capacitance ratio
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How to achieve the minimum jitter peaking

• For given m, there exists the minimum jitter
  peaking
• --the minimum jitter peaking can be viewed
  as a function of m JP(m)
• The minimum jitter peaking under a given m is
  achieved only by using a proper ?
• --? should be a function of m ?m(m)

JP(m)

• ?m(m)

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Sampling effect of phase detector

• The phase detector has sampling effect,
  especially when its rate is not much higher than
  the loop cut-off frequency
• Approximate TF of phase detector

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Jitter Peaking w/ PD Sampling Effect

• It causes the jitter peaking worse
• when ? is very small, jitter peaking decreases
  when ? increases
• when ? becomes larger than ?m, jitter peaking
  increases with ?
• when ? is larger than ?m2, jitter peaking
  decreases when ? is increased further

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JP(m) and ?m(m) with sampling effect
JP(m) with sampling effect
?m(m) with sampling effect
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Tables of JP(m) and ?m(m) for practical design
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Design procedures of charge pump PLLs for
jitter transfer characteristic optimization

1. Decide the maximum tolerated jitter peaking and
   find capacitance ratio m using JP(m).
2. Use ?m(m) to find the optimal damping ratio value
   ?m
3. Decide ?n according to the application, choose
   reasonable KVCO, and calculate Ip, R, C1 and C2
4. Use time domain simulation to verify that the
   expected jitter transfer performance can be
   achieved

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Design example

• Target to design a 2.5GHz CP PLL, meet the
  jitter specification
• Design parameters m0.005 and ?5.0
• Simulation result jitter peaking is only 0.078dB
  

Jitter transfer characteristic of the designed
PLL
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More Discussion on Loop Transfer Function

• The above discussion suggests to use very small m
  to meet the jitter peaking
• However, if m is too small, the effect of the
  second capacitor can even be ignored
• Compromise should be made between jitter peaking
  and other performance

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Charge pump PLL calibration

• Purpose make the loop transfer characteristic
  meet the spec
• Calibration types
• Component calibration
• Loop calibration

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Charge Pump Calibration

• Purpose minimize the mismatching between UP and
  DOWN current
• Method switch small current sources

UP
UP
Iup
Iup
ICAL
ICAL
ICAL
ICAL

Idn
Idn
DN
DN
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Charge Pump Calibration Procedure

• Use the UP or Down current to charge/discharge a
  capacitor
• Compare the time difference and calculate the
  calibration code

Ref CLK
UP
Counter
Vref
Iup
R/S
Comparator
Idn
DN
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VCO Coarse Tuning

• Purpose to speed frequency tracking
• Method make use of the coarse tuning
  functionality of the VCO
• When extreme high frequency range is desired,
  double VCOs can be used to help achieve fine
  frequency tuning resolution

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VCO Coarse Tuning Procedure

• Apply different coarse tuning voltage (output
  from a low resolution coarse tuning DAC)
• Measure VCO output frequency respectively
• Compare to the reference frequency
• Write the desired DAC code into register

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Time Constant Calibration

• Purpose calibrate the loop transfer function
  time constant so that the 3-dB frequency meets
  the spec
• Method switch small CAL capacitors

CCAL
CCAL
CCAL
CCAL

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Time Constant Calibration Procedure
Ref CLK
R
Counter
Vref
Vref
R
Vx
C
Comparator
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Loop Gain Calibration

• Purpose calibrate the loop transfer gain to the
  desired value
• Method switch different charge pump output
  current (KVCO is not changeable usually)