Design of a Phase Locked Loop

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Design of a Phase Locked Loop ECE 453 Team
Members Joshua Rubin Final Project Rishi
Sinha Xiao-wen Lu Adviser Chilezie
Nnadi Prof. Apsel December 2nd 2005
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What is a PLL?

• A PLL is a closed loop feedback control system
  that maintains a constant phase difference
  between its input ref. signal and its output.

• A PLL is a closed loop feedback control system
  that maintains a constant phase difference
  between its input ref. signal and its output.
• Used in Frequency synthesizers,
  modulators/demodulators in wireless
  communication, synchronizers and multiplexers.

PLL output Vout Øout(t)
Ref. Input Vin Øin(t)
PFD
CP
LPF
VCO
Feedback signal
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PFD What is a PFD?

• The PFD detects the ?Ø between the input and
  output signals of the PLL and outputs UP and
  DOWN voltage pulses for a ve ?Ø and ve ?Ø
  respectively.

V2(t)
V1(t)
Switch A
QA
Vctrl
Switch B
QB
CP
PFD
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PFD How does it operate?
? t2 SA on-time
QB
QA
V2(t)
V1(t)
VIH
? t1 ?Ø
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Operation of Charge Pump / LPF
Schematic
QA
Vcontrol
C2
Rp
QB
Cp
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Components of CP/LPF

• Inverter and Pass Gate should provide similar
  delays.
• PMOS and NMOS current sources
• PMOS and NMOS switches
• Output resistance of charge pump and C2 form a
  low pass filter.
• Cp stores the charge to define Vcontrol.

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CP/LPF Waveforms
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CP Qualitative Analysis
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VCO Crossed-Coupled LC Oscillator
Mathematic Model
LC Tank

• Oscillation Condition
• Feedback View
• Negative Resistance view

There is no power loss.
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Schematic

• Using differential cross-coupled PMOS
• Change the frequency of VCO by changing the
  capacitance-Varactor

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Calculating KVCO
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Performance of VCO
Peak-Peak at Vc2.5V 3.058V Peak-Peak at Vc0
V 1.42V Tuning range598MHz658MHz 60MHz
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Transfer Function
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Simulation Results Control Voltage
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Simulation Results
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PLL performance

• Locking Range 625 655 MHz
• Locking time 1.0u sec

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References

• 1 Behazd Razavi, Design of Analog CMOS
  Integrated Circuits
• 2 Simon Haykin, Communication Systems