Introduction of CDR, Architectures and Circuits

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Introduction of CDR, Architectures and Circuits

• Peiqing zhu

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Introduction of CDR Application
Fig 1.1 Block level architecture of 10Gb/s SONET
receiver
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1). OC-192 receiver architecture that the
interface between the optical and electronic
worlds 2) The photodiode convert the incoming
NRZ optical pulses of a single 10Gb/s channel
into an electrical current. 3) The
transimpedance (TZ) amplifier converter these
current into voltage. 4). AGC provides
additional amplification while compensating for
variations in the received signal power. 5). The
clock required to retime the incoming
synchronous data stream is recovered from the
received data stream by the clock recovery block
(CDR). 6) The recovered clock is then applied
to a time-division demultiplexer (DEMUX) in order
to separate the 10Gb/s stream into multiple,
lower speed channels. Typical DEMUX ratios
are14, 18 and 116.
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Dual Loop CDR System

• Fig. 1.2 Generic block level architecture of PLL
  based CDR.

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Clock and Data Recovery System Specifications

• Jitter generation measure of the jitter created
  by the CDR when it is locked to a jitter free
  reference clock
• Jitter transfer function the ratio between
  output jitter and input sinusoidal jitter at
  various input jitter frequencies
• Jitter tolerance the peak-to-peak amplitude of
  sinusoidal jitter applied to the data input that
  causes a 1-dB power penalty.

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The CDR jitter transfer function

• Figure 1.3 OC-192 Jitter transfer specification.

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The CDR jitter tolerance specification
Figure 1.4 OC-192 Jitter Tolerance specification.
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Introduction of the full-rate and half rate CDR
timing diagram
Fig. 1.5 Waveform for Full-rate and Half-rate
CDR.
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The PLL based CDR Architecture
The PLL based CDR is composed of PFD, VCO and
Charge Pump
Figure 1.6 PLL architecture for clock recovery
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Introduction of CDR building block(PFD/FD,
Charge Pump)

• PFD Linear Phase Detector, Binary Phase Detector
  and Sampling Hold Phase Detector.
• Charge Pump
• Frequency Detector Quadricorrelator frequency
  detector ,Rotational frequency detector etc.

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Introduction of CDR building block (VCO)
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Rogers10 Gb/s CDR
Figure 1.7 Dual Loop, Half-Rate CDR circuit
block.
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Phase Detector block
Fig. 1.20. half rate early/later phase detector
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Voltage Controlled Oscillator
Figure 1.19 LC delay line ring oscillator
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Charge Pump and Common Mode Feedback Design
Figure 1.20 Charge pump and common mode feedback
with loop filter
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CDR Performance
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Afshin Rezayee designed two version 10 Gb/s CDR
circuit

• The first version architecture single loop,
  half-rate line phase detector

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Linear Phase detector
Figure 1 Half-Rate Linear Phase Detector
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Charge Pump and loop filter
Figure 3 Charge Pump and loop filter
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VCO For the CDR
Figure 4 Coupled two-stage ring oscillator
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Summary of CDR Performance

Table-1 Summary Performance
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The second version architecture
Figure 5 Dual Loop Half-Rate CDR overall block
diagram
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Half-Rate Alexander Phase Detector
Figure 6 Half-Rate Alexander Phase Detector
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Half-Rate Frequency Detector
Figure 8 Half-Rate Frequency Detector
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VCO design
Figure 10 The coupled two-stage ring oscillator
with coupled buffers
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Charge-Pump
Figure 11 Charge-pump schematic
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CDR Performance
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Jafar Savoj two versions 10 Gb/s CDR

• First version single loop, half rate linear
  phase detector

Figure 1 Half-rate CDR architecture
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Voltage Controlled Oscillator
Figure 2 Three-stage ring oscillator
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Half-Rate Linear Phase detector
Figure 3 (a) Phase Detector (b) Operation of the
circuit
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Charge Pump and Loop Filter
Figure 5 Charge pump and loop filter
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CDR Performance
Table 1 CDR performance summary
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The second version

• Architecture Dual loop, Half-Rate early/later
  phase detector.

Figure 6 Dual Loop, Half-Rate CDR Architecture
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Voltage Controlled Oscillator
Figure 7 Four-stage LC-tuned ring oscillator
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Phase and Frequency Detector
Figure 8 Phase and Frequency Detector
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Charge Pump
Figure 10 Charge Pump
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Performance
Table 2 CDR performance summary
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Jri Lee 40 Gb/s CDR

• Architecture single loop, quadrature rate
  Alexander phase detector using the 0.18 CMOS
  technology

Figure 1 Quarter-rate CDR architecture
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Voltage Controlled Oscillator
Figure 2 Multiphase differential oscillator
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Quarter-Rate Anlexander Phase detector
Figure 3 (a) Phase Detector (b) Operation
timing diagram of the circuit
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Converter and Loop Filter
Figure 5 V/I Converter
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Performance
Table 1 CDR performance summary
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Mehrdad Ramezani 10G CDR Implementation
Architecture Dual Loop, Half-Rate Bang-Bang
Phase Detector
Fig.1. 1 Block Diagram of the 10Gb/s PLL-based
CDR
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Phase Detector
Fig. 1.2 Schematic of the 10 Gb/s CDR Phase
Detector
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Frequency Detector
Fig.1. 4 Block Diagram of the Frequency Detector
(rotational methodology)
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Charge Pump and Loop Filter
Fig. 1.5 Schematic of the Charge-Pump and Loop
Filter
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Voltage Controlled Oscillator
Fig. 1.6 Schematic of Four Stages Fully
Differential VCO.
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V/I Converter and Biasing
Fig. 2.5 Schematic of the V/I Converter and
Biasing Circuit
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Performance
Table 2 10Gb/s CDR Performance
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Comparison of CDRs
Table 5.7 CDR performance caparison
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Conclusion

• Dual loop, half-rate CDR architecture is widely
  used for its high performance and no unlock
  problem.
• For the building block
• 1) Phase detector Binary phase detector
• 2) Frequence detector Rotational frequency
  detector.
• 3) VCO Differential 4-stages delay cell
  oscillator or differential 2-stages LC oscillator