7 Memory and Programmable Logic

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7 Memory and Programmable Logic
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INTRODUCTION
Memory Unit a collection of cells capable of
storing a large quantity of binary information
RAM(random access memory) read and write
operation ROM(read only memory) only
read operation
Programmable Logic Device PLD(programmable
logic device) PLA(programmable logic array)
PAL(programmable array logic) FPGA(field
programmable gate array)
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RANDOM-ACCESS MEMORY

• The address lines select one particular word.
• A decoder inside the memory accepts this address
  and opens the paths needed to select the word
  specified.
• word an entity of bits that move in and out of
  storage as a unit,
• 16-bit word, 32-bit word

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1024x16 Memory
10 address lines and 16 bits in each word.
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Timing Waveforms cycle time the time required to
complete a write operation suppose that clock
frequency 50MHz cycle time lt 50ns
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Types of Memories Random-access memory same
access time Sequential-access memory variable
access time(magnetic disk, tape) Static
RAM(SRAM) latches easier to use shorter read
and write cycle Dynamic RAM(DRAM) stores the
binary info. in the form of electric charges on
capacitors. The capacitors must be periodically
recharged by refreshing. reduced power
consumption larger storage capacity in a single
chip Volatile nonvolatile
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Internal construction of RAM

• The equivalent logic of a binary cell that stores
  one bit of information
• The binary cell stores one bit in its internal
  flip-flop
• It has three inputs and one output. The
  read/write input determines the cell operation
  when it is selected.

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Diagram of 4 x 4 RAM
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Coincident Decoding

• Two-Dimensional Decoding Structure for a 1k-word
  Memory
• a 10x1024 decoder
• 1024 AND gates
• two 5 x 32 decoders
• 64 AND gates

If the word address is 404, X01100 (12) and
Y10100(20).
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Address Multiplexing

• To reduce the number of pins in the IC package,
  designers utilize address multiplexing whereby
  one set of address input pins accommodates the
  address components.
• Since the same set of pins is used for both
  parts of the address, the size of the package is
  decreased significantly.
• Row Address Strobe
• Column Address Strobe

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READ-ONLY MEMORY
5 X 32 decoder has 32 AND gates and 5 inverters.
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ROM Truth Table(Partial)
A7(I4,I3,I2,I1,I0) ?(0,2,3,...,29)
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Combinational Circuit Implementation
A7(I4,I3,I2, I1, I0)?(0,2,3,,29)
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Input-gt00011(3) Others-gt all 0 Output-gt10110010
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Design a combinational circuit using a ROM.
input 3-bit number, output square of input
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Combinational PLDs
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PROGRAMMABLE LOGIC ARRAY
F1ABACABC F2(ACBC)
Programmable OR array
Programmable AND array
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Implement the following functions with a PLA
F1(A,B,C)?(0,1,2,4), F2(A,B,C)?(0,5,6,7)
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PROGRAMMABLE ARRAY LOGIC
PAL-With a fixed OR array and a programmable AND
array. -Not as flexible as the PLA(Only the AND
gate are programmable.) PAL with 4 inputs, 4
outputs, and 3-wide AND_OR Structure
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Implement the following functions with a PAL
w(A,B,C,D)?(2,12,13), x(A,B,C,D)?(7,8,9,10,11,1
2,13,14,15) y(A,B,C,D)?(0,2,3,4,5,6,7,8,10,11,15)
, z(A,B,C,D)?(1,2,8,12,13)
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Fuse Map for PAL
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SEQUENTIAL PROGRAMMABLE DEVICES

• Sequential(or simple) Programmable Logic Device
  (SPLD)
• Complex Programmable Logic Device(CPLD)
• Field Programmable Gate Array(FPGA)

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CPLD-a collection of individual PLDs
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FPGA(Field Programmable Gate Array) a VLSI
circuit that can be programmed in the users
location. -look-up tables,multiplexes,gates, and
flip-flops