Communication Engineering N Phase Locked Loops (PLLs)

1
Communication Engineering N Phase Locked Loops
(PLLs)

• PLL Topics
• PLL model and qualitative description
• PLL components
• Linear PLL analysis by D.E.s and Laplace
• PLL applications
• Case Study of PLLs and FDMA FM Stereo
  Broadcasting
• Refs Text 4-14 5-7

2
PLL Model
v1(t)
Phase Comparator
LPF
Input signal eg A cos(wct ?i(t))
VCO
v2(t)

• Qualitative Description of Operation
• VCO adjusts its frequency and phase in order to
  minimise the difference between its phase and the
  phase of the input signal. Provided that the
  input signal doesnt change too fast the VCO
  stayed locked to the input. Thus the PLL acts
  like a narrow band tracking filter.

• PLLs have a large number of applications
  including FM/FSK demodulation frequency
  synthesis synchronisation
• Depending on the application, either the VCO
  input control voltage or its output may be used
  as the PLL output signal.

3
PLL Component Models Summary
?o(t)
VCO wo(t) kvv2(t) so d?o(t) /dt kvv2(t)
where kv units are radians/sec/V
v2(t)
VCO
Loop Filter v2(t) v1(t) h(t) where h(t)
is the filter impulse response
v2(t)
v1(t)
LPF
v1(t)
For product mixer v1(t) kd sin(?i(t)-?o(t)) wher
e kd units are V/radian Linear Region let e
?i-?o if elt 1 then v1(t) kd e(t)
Phase Comparator
?i(t)
?o(t)
4
Linearised PLL Analysis Summary

• These analysis methods can be applied in the
  linear region of PLL operation
• Via Differential Equations
• considered 1st order loop with phase step input
  
• Via Laplace Transforms
• derived s-domain TFs for phase_error/input_phase
  (gives a high pass response), VCO_control
  voltage/input_phase and VCO_phase/input_phase
  (which gives a low pass response)
• considered 1st and 2nd order loops with phase
  step and frequency step inputs

5
First order loop summary

• No steady state error for phase step
• steady state phase error (for ? step) with error
  of ?/(kvkd) ?s/ ?3dB
• to stay in linear operating range ?slt ?3dB
• ?3dB sets speed of lock and steady state phase
  error
• as ?3dB increase the loop responses more to
  noise therefore H(s)1 not usually employed
• kvkd also set pull-in range

6
PLL Applications and Case Studies Summary
Application FM Demodulation via analysis of the
steady state transfer function see text p.274,
275 Application Frequency Synthesis architectu
re of a PLL frequency synthesiser text Fig
4-25 Case Study of FDM and PLLs FM Stereo
Broadcasting text section 5-7, 5-8 Tx and Rx
block diagrams Case Study of Frequency
Synthesis PLL frequency synthesiser (see
SAA1057 handout) and Case Study 4