Release Consistency

1
Release Consistency

• Yujia Jin
• 2/27/02

2
Motivations

• Place partial order on memory accesses for
  correct parallel program behavior
• Relax partial order for memory accesses overlap
• Tradeoff between programmer productivity and
  processor performance

3
Basic Assumptions

• Uniprocessor control and data dependences are
  respected
• Memory coherence
• Read write to same the address is serialized

4
Previous Consistency Models

• Sequential Consistency (SC)
• Each processor runs in program order
• Operations of all processors serialized
• Processor Consistency (PC)
• Same as SC except
• Read can bypass write before write is performed
• Non-atomic write
• Weak Consistency (WCsc)
• Memory access cannot be reordered pass
  synchronization accesses
• Synchronization accesses are sequential
  consistent

5
Access Classification
Shared access
Competing
Non-Competing
synchronization
Non-synchronization
acquire
release
6
Key Observations

• Acquire
• Getting permission from other processors for
  subsequent memory accesses
• Previous memory accesses can be overlapped
• Release
• Giving permission to other processors for
  previous memory accesses
• Subsequent memory accesses can be overlapped

7
Release Consistency

• Cannot start memory access before previous
  acquires are performed
• Cannot start release access before previous
  memory accesses are performed
• Competing accesses in PC

8
Comparison
acquire
acquire
acquire
acquire
load
load
load/store load/store
load/store load/store
load
load
release
release
release
release
load/store load/store
load/store load/store
store
store
store
store
nsync store
nsync store
nsync store
nsync store
load/store load/store
load/store load/store
load
load
acquire
acquire
acquire
acquire
store
store
SC
PC
load/store load/store
WCsc
load/store load/store
RCpc
release
release
release
release
9
Properly-Labeled Program
sharedL

• Add enough syncL lables such that there is an
  appropriate syncL separating any possible pairing
  of two conflicting memory accesses from different
  processors, where at least one of the access is
  ordinaryL
• Competing ? specialL
• (shared access) ? sharedL
• Less conservative label gives better performance
• Label by compiler or by programmer thourgh
  predefined synchronization constucts

ordinaryL
specialL
nsyncL
syncL
acqL
relL
10
Implementation

• Use fence operations to block memory accesses
• Conditional block, only if some relevant memory
  accesses have not performed
• Three types of fence, full, write, immediate
• Fence operations is flexible, can implement SC,
  PC, WC, RC,

11
Discussion

• One step closer to message passing?
• With the additional complexity, how much
  improvement do we get?