A Linear Programming Based Static Power Optimization Scheme for Digital CMOS Circuits

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A Linear Programming Based Static Power
Optimization Scheme forDigital CMOS Circuits

• Course Project AMSC-662
• Vishal Khandelwal
• Department of Electrical and Computer
  Engineering,
• University of Maryland-College Park.

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Introduction

• Optimization forms a key step in all forms of
  engineering and science problems.
• There is more demand for performance and problem
  constraints are getting tighter.
• In VLSI design, technology scaling has caused
  optimization to become even harder.
• VLSI Chips are now used in almost every
  application ranging for electronic gadgets to
  microwaves to cars.

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Introduction

• The complexity of chips is increasing
  tremendously.
• The Intel Pentium-4 chip has over 50 million
  transistors.
• Optimization at such magnitude is a VERY hard
  problem.
• One can optimize for area, power, performance,
  reliability and many other such metrics that are
  inter-dependent.

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Introduction

• Think about a simple problem as optimizing area
• Try and fit a 100,000 rectangles of different
  shapes into minimum area.
• Now imagine what would happen if it were millions
  of rectangles!!!!!
• The solution space is very large and its not
  possible to traverse it fast and get a provably
  good solution.

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Introduction

• VLSI Design Automation provides sophisticated
  tools for a designer to create his chips without
  getting involved in these complexity
• Given Specification ? Get a layout level chip
  ready to be fabricated!
• VLSI Design flow involves complex optimization at
  every step.

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Introduction

• In this work we look at one such optimization
  step of static power minimization.
• Static or Leakage power is the power that is
  consumed in a circuit even when it is supposed to
  be OFF.
• Cell Phones, PDAs and other mobile applications
• In the current technology leakage is as much as
  40 of total power and hence is significant.

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Introduction

• There are several schemes for leakage power
  reduction. We pick one such popular scheme called
  MTCMOS.
• This involves placing Sleep Transistors at
  logic gates and sizing of sleep transistors to
  controls their speed as well as leakage ( this is
  a trade-off).
• We look at a novel linear programming formulation
  to solve the optimal sizing problem of sleep
  transistors.

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MTCMOS Design

• Put high-threshold sleep transistors in series
  with the low-threshold logic gates.

High Threshold Sleep Transistors
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Optimal Sizing Algorithm
TA1

• Problem
• Given a circuit with fine-grained sleep
  transistors placed and a delay constraint at the
  output, size the transistors optimally for
  minimal leakage under this delay constraint

TR1
TA2
TR2
TA3
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Possible Solutions

• Iterative Monte-Carlo style scheme
• Solution Space is too large, will take long time
• Slow everything down by the same ratio
• Done by other existing schemes but this is a
  sub-optimal solution
• Dynamic Programming based algorithm
• Generally an expensive solution in terms of
  runtime.

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Motivation

• Efficient slack utilization at non-critical gates
  to reduce their leakage
• Non-uniform sizing of sleep transistors

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MTCMOS Design

• Gate Delay
• The ON Current in active mode is given by
• The Sub-Threshold leakage current in standby mode
  is given by

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MTCMOS Design

• Hence, there is a trade-off between gate leakage
  and gate delay
• Theorem Gate Leakage is a convex function of
  gate delay.

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Optimal Sizing Algorithm
Du
Dv
du
dv
U
V
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Optimal Sizing Algorithm

• All the constraints are linear.
• Objective function is convex and separable.
• D. Hochbaum and J. Shanthikumar, Convex
  Separable Optimization is not much harder than
  Linear Optimization, In Journal of the ACM, Vol.
  37, No. 4, 1974.
• Hence, our sizing algorithm is polynomial time
  optimal!

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Experimental Results

• The scheme was implemented in SIS.
• All parameters taken for 0.18 micron technology.
• VtH 500mV, VtL 350mV, ION 300uA.
• Experiments done with ISCAS benchmarks in SIS.
• The sizing formulations were solved using CPLEX.

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Experimental Results
For 5 slowdown, 69.0 improvement over fixed
delay using optimal sizing
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Results
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Conclusion and Future Work

• Presented a novel linear programming approach to
  solve the static power minimization problem
  through OPTIMAL sizing of sleep transistors in
  polynomial time.
• This formulation is a part of a research paper
• Vishal Khandelwal and Ankur Srivastava, Leakage
  Control Through Fine-Grained Placement and Sizing
  of Sleep Transistors, Proceedings of IEEE/ACM
  Conference on Computer-Aided Design Nov. 2004.
• Problem Linear Programming is slow for very
  large circuits. So we need to develop efficient
  partitioning schemes to solve smaller
  sub-problems.

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• Thank you for your attention!
• Questions?