Veljko Radeka, Sergio Rescia, Gianluigi De Geronimo

1
Induced Gate Noise in Charge Detection
Veljko Radeka, Sergio Rescia, Gianluigi De
Geronimo Instrumentation Division, Brookhaven
National Laboratory, Upton, NY
2
Charge detection - capacitive signal source
Drain current noise
Induced gate noise
With a capacitive signal source induced noise
voltage spectrum is white ? both drain and gate
noise can be referenced to the gate as an
equivalent series noise resistance. Neglecting
correlation
(Ref. 3)
For power optimized CMOS Cgs(1/4)Cin , and
the increase in Req is lt 2.5. The effect of
correlation is less than 10.
3
Real Term in the Gate Admittance
unity gain frequency electron transit
time
4
Real (Damping) Term in the Control Electrode
Admittance of all Charge Controlled Devices
transit time
Charge in transport
Transconductance
Unity gain frequency
Control electrode admittance
At high frequencies
phase shift
a1
Damping of tuned circuits by control electrodes
with zero dc current observed in 1930s (Ref. 1)
phase shift
5
Gate Induced Noise vs f and fT
fT(GHz) gm(mS) Cgs(fF) 4
10 330 8
14 220 16 18
140 26 23
90 45 28 68
NF1dB 0.25dB
Long L Short L d 4/3
(lt3?)g 2/3 lt1.2
Data from C.-H. Chen,et al., IEEE Trans.
Electron devices,48, 2884(Dec. 2001)
6
Noise Enhancement with VDS in DSM MOSFETS?
Drain current thermal noise vs VDS
Gate current noise vs VDS
No significant enhancement at L0.18 mm !
From A. J. Scholten et al., IEEE Trans. Electron
Devices, 50, 618 (March 2003)
7
White noise gamma factor vs VDS and L
2/3 g lt 1.1
Gradual channel Velocity saturation
region region
From C.-H. Chen and M. J. Deen, IEEE Trans.
Electron Devices, 49, 1484(Aug. 2002)
Noise model Channel Length Modulation (CLM)
8
Equivalent Series Noise Resistance for Charge
Detection (Capacitive Source)
Transconductance
Gate induced
Induced into gate (shielded by the inversion
layer!?)
Gate resistance
Substrate resistance
1
Intrinsic channel noise
Ref. 9
9
Acknowledgements
Numerous discussions with Anand Kandasamy,
Paul OConnor and Pavel Rehak are gratefully
acknowledged.
10
References 1. Ferris, W. R., Proc. IRE,
24, No. 1 (1936) 82 2. Van der Ziel, A.,
Proc. IEEE, 51 (1963) 461 3. Radeka, V.,
IEEE Trans. Nucl. Sci., NS-11 (1964) 358 4.
Manku, T., IEEE Journal of Solid-State
Circuits, 34, No. 3 (1999) 277 5
Signoracci, L., et al., Solid-State Electronics,
45 (2001) 205 6. C.-H. Chen, et al., IEEE
Trans. Electron Devices, 48, (Dec. 2001) 2884 7.
C.-H. Chen and M.J. Deen, IEEE Trans.
Electron Devices,
49, (Aug. 2002) 1484 8.
A. J. Scholten, et al., IEEE Trans.
Electron Devices, 50, (March 2003) 618 9.
S. V. Kishore, et al., IEEE 1999 Custom
Integrated Circuits Conference, p.365