PowerPoint Sunusu

1
A High Data Rate X-Band Transmitter with an
Efficient Solid State Power Amplifier   by Dr.
Ozlem A. Sen, Celal Dudak, Hacer K. Sunay,
A.Neslin Ismailoglu, Tunahan Kirilmaz TUBITAK-BIL
TEN Middle East Technical University,ANKARA,TURKIY
E
 
2
Contents

• INTRODUCTION Transmitter Overview
• Design and Realisation of Transmitter
• Baseband
• IF stage
• RF Stage
• Power Amplifier
• Design
• Simulation
• Realization and measurements
• Conclusion and Future Work

3
Introduction Transmitter overview

• Low Earth Orbit (LEO) Satellite Tranmitter
• Data rates up to 100 Mb/s with BPSK/QPSK/OQPSK
  modulation
• Linearity requirements
• 7W (38.5 dBm) output at 8.2 GHz
• Efficiency-linearity trade off

4
Block Diagram of Transmitter
5
General Properties of Transmitter

• 680 km altitude orbit
• Supporting maximum 100Mbs data rate at min. 30
  elevation angle
• 10-6 BER
• 4.5 m dish antenna at the ground station
• Patch antenna structure at 8.2 GHz with maximum
  gain at 30 elevation angle
• ?7 W output power

6
Baseband

• Baseband data processing including channel coding
• Implementation on FPGA, Xilinx Virtex-II
• Conversion of digital I Q data into analog
  through high speed DACs
• Direct conversion into IF through direct
  quadrature modulators

7
Baseband-Coding

• Channel Coding nested structure
• Outer code Reed Solomon with (255,223,33)256,
• for burst errors due to multipath fading
• Inner code a convolutional code with rate (1/2)
• For random errors
• with a moderate
• bandwidth expansion

8
Modulation

• Supporting 25/50/100 Mbs for BPSK/QPSK/OQPSK
  modulation schemes
• High data rate considering BW constraints imposed
  by satellite communication
• Maximum data rate for fixed ground stations,
• Sufficient data rate for mobile communications
• Digital baseband pulse shaping with RRC filter
• Direct Quadrature modulation to S-band

9
Realisation, baseband and DQM

• Baseband data processing including channel coding
  
• Implementation on FPGA, Xilinx Virtex-II
• Post synthesis timing analysis demonstrated that
  100 Mbps data rate for QPSK signal is possible
• DACs and direct quadrature modulation is realised
  
• Since baseband data processing is not implemented
  on FPGA, this part is imlemented using the data
  from MATLAB simulations and pattern generator
  (limits the data rate to 72 Mb/s)

10
Realisation Results, after DQM
40 MHz clock (20Mb/s)
134 MHz clock (72Mb/s)
11
Realisation Results, after DQM

• dddd

12
Realisation Results, IF Stage

• ddddd

40 MHz clock (20 Mb/s)
134 MHz clock (72 Mb/s)
13
Realisation Results, IF Stage

• dddd

14
RF Stage

• BPF
• For harmonic suppression at the mixer output
• Insertion loss is not critical
• Can be realized with microstrip lines
• Design and simulations are concluded, final
  simulations are carried on Sonnet, 3D simulator
• Realised on Rogers TMM6 substrate

Fujitsu FLM7785-12F
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RF Stage, PA

• Two stage narrowband power amplifier supports
• 180 Mbps data rate at 8.2 GHz,
• 7W (38.5 dBm) output power,
• gain of 20.5? 0.6 dB in 8.17-8.265 GHz bandwidth
• the efficiency is 26.
• The first stage of the power amplifier
• Class AB amplifier
• output power 30 dBm
• efficiency 22.

Fujitsu FLM7785-12F
16
RF Stage, PA

• The second stage
• class AB amplifier
• 38.5 dBm output
• 35 efficiency
• drain current decreases with the decrease in the
  input power so that efficiency degradation in the
  low input power is limited.
• especially important since it increases
  efficiency without sacrifying linearity for the
  modulations with high peak to average ratio.

Fujitsu FLM7785-12F
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PA, Design and Simulations

• Transistors internally matched,
• better to use input and output matching circuitry
  for both of the stages,
• this matching circuitry effects
• the efficiency of the power amplifier
• the maximum power avaliable from the power
  amplifier
• Commecial transistors
• Lower drain voltage (8.8V instead of 10V) to
  increase relaibility

18
PA, Design and Simulations

• Matching circuitries for the first and second
  stage
• Using S-parameters of the FLM7785-4F and
  FLM7785-12F internally matched transistors from
  Fujitsu Quantum Devices,
• matching circuitry layouts on the high frequency
  laminate, Rogers-TMM6 / Thickness 0.05 /
  Dielectric constant 6.
• Simulations of matching circuitry and harmonic
  termination effects are carried out on SonnetÒ,
  considering probable loading of bias circuitries
  .

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PA, Design and Simulations

• Matching circuitries for the first and se
• stage
• Using S-parameters of the FLM7785-4F
• and FLM7785-12F internally matched transistors
  from Fujitsu Quantum Devices,
• matching circuitry layouts on the high frequency
  laminate, Rogers-TMM6 / Thickness 0.05 /
  Dielectric constant 6.
• Simulations of matching circuitry and harmonic
  termination effects are carried out on SonnetÒ,
  considering probable loading of bias circuitries
  .

First Stage
Second Stage
20
PA, realisation

• matching circuitries are not at the desired
  frequency
• the parasitic effects of the package of the
  transistor,
• slight differences between the specified
  S-parameters of the transistors due to the bias
  conditions,
• effects that are not included in the simulations.

21
PA, realisation

• Especially at high power there is grounding and
  shielding problem which limits the gain of the
  second stage to 5dB

22
PA, realisation

• Different matching circuitries are investigated,
• the one which shows short circuit at the second
  harmonic limits the maximum output power to
  38dBm.
• Optimum matching considering both fundamental and
  harmonic. It has
• an output up to 41 dBm
• the drain current decreases with the decrease in
  the input power which is desirable for high peak
  to average value signals.

23
PA, realisation

• impedance at 8.2 GHz
  impedance at 16.4 GHz

24
PA, measurement results

• Output Power Output power Output power
  ACP Output power ACP
• DA 1ststage
  2nd stage 2nd stage 2nd stage
  2nd stage
• (dBm) (dBm) Id2.2A
  (dBm) Id2.2A (dBm) Id2.5A (dBm) Id2.5A (dBm)
• 8.3 19.9 26.8 lt-33 27.4
  lt-33
• 13.3 24.9 31.8 lt-33 32.4
  lt-33
• 16.3 27.9 34.8 lt-33 35.2
  lt-33
• 18.3 29.9 36.8 lt-33
  37.1 -31
• 19.3 30.9 37.8
  lt-33 38.1
  -31
• 20.3 31.9 38.8 -32.3 39.0
  -30
• 21.3 32.9 39.7 -30.0 39.8
  -28.3
• 22.3 33.9 40.2 -27 40.3
  -25.2
• 23.3 34.6 40.5 -24.7 40.6
  -23.6
• 24.3 35.0 40.7 -23.0 40.8
  -22.4
• 25.2 35.5 40.9 -21.0 41.0
  -21.0
• 25.8 35.7 41.1 -19.0 41.1
  -19.0

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PA, measurement results

• dddddd

26
PA, measurement results

• dddddd

27
PA, measurement results

• dddddd

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Conclusions

• State of the art transmitter with QPSK/OQPSK
  modulation schemes at 100 Mb/s data rate
• Designed with commercial of the shelf components,
  low cost
• Solid state power amplifier instead of TWTA,
• Low weight (important for LEOs)
• Higher linearity (important for QPSK)

29
Conclusions

• Two stage power amplifier structure supports
• 180 Mbps data rate at 8.2 GHz,
• 7W (38.5 dBm) output power,
• Gain 20.5? 0.6 dB in 8.17-8.265 GHz bandwidth
• Overall efficiency is 26.
• The first stage Class AB amplifier,
• output power of 30 dBm,
  efficiency of 22.
• The second stageClass AB amplifier,
• 38.5 dBm output and
  35 efficiency

30
Conclusions

• Drain current decreases with the decrease in the
  input power so that efficiency degradation in the
  low input power is limited.
• Especially important since it increases
  efficiency without sacrificing linearity for the
  modulations with high peak to average ratio.

31
Future Work
Zo _at_ fundamental
freq. high impedance _at_ 2nd harmonic lowimpedanc
e _at_ 3rd harmonic .