CS 140 Lecture 12 Standard Combinational Modules

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CS 140 Lecture 12Standard Combinational Modules

• Professor CK Cheng
• CSE Dept.
• UC San Diego

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Part III - Standard Combinational Modules

• Decoder Decode address
• Encoder Encode address
• Multiplexer (Mux) Select data by address
• Demultiplexier (DeMux) Direct data by address
• Shifter Shift bit location
• Adder Add two binary numbers
• Multiplier Multiply two binary numbers

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Interconnect Decoder, Encoder, Mux, DeMux
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1. Decoder

• Definition
• Logic Diagram
• Application (Universal Set)
• Tree of Decoders

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1. Decoder Definition
EN (enable)
y0 y1 y7
0 1 2 3 4 5 6 7
0
I0
. .
1
I1
I2
2
n to 2n decoder function
2n outputs 23 8
n inputs n 3
yi 1 if En 1 (I2, I1, I0 ) i yi 0
otherwise
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1. Decoder Definition

• N inputs, 2N outputs
• One-hot outputs only one output HIGH at once

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Decoder Logic Diagram
yi mi En
En
y0 1 if (I2, I1, I0 ) (0,0,0) En 1
I0
y0
I1
I2
I0
y1
I1
I2
. .
I0
y7 I0I1I2En
y7
I1
I2
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Decoder Application universal set Decoder, OR
Implement functions f1(a,b,c) Sm(1,2,4)
Example
f2(a,b,c) Sm(2,3), and
f3(a,b,c) Sm(0,5,6)
with a 3-input decoder and OR gates.
y1
y2
y4
f1
y2
y3
f2
y0
y5
y6
f3
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Decoders

• OR minterms

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Tree of Decoders
Implement a 4-24 decoder with 3-23 decoders.
y0 y1 y7
0 1 2 3 4 5 6 7
d
I0
c
I1
b
I2
y8 y9 y15
0 1 2 3 4 5 6 7
I0
I1
I2
a
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Tree of Decoders
Implement a 6-26 decoder with 3-23 decoders.
En
En
y0
D0
I2, I1, I0
y7
y8
I5, I4, I3
D1
I2, I1, I0
y15


y56
D7
I2, I1, I0
y63
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2. Encoder

• Definition
• Logic Diagram
• Priority Encoder

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2. Encoder Definition
En
I2n-1I0
yn-1 y0
A
Encoder Description
En
At most one Ii 1. (yn-1,.., y0 ) i if Ii 1
En 1 (yn-1,.., y0 ) 0 otherwise. A 1 if
En 1 and one i s.t. Ii 1 A 0 otherwise.
I0
0 1 2 3 4 5 6 7
y0
0 1 2
y1
y2
I7
3 outputs
A
8 inputs
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Encoder Logic Diagram
En
y0
I1
I3
I5
I7
En
y1
I2
I3
I6
I7
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Encoder Logic Diagram
En
y2
I4 I5 I6 I7
En
A
I0
I1
.
.
I6
I7
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Priority Encoder Definition
Description Input (I2n-1,, I0), Output (yn-1
,,,y0)
(yn-1 ,,,y0) i if Ii 1 En 1 Ik 0
for all k gt i.
Eo 1 if En 1 Ii 0 for all i, Gs 1 if En
1 i s.t. Ii 1.
E
(Gs is like A, and Eo tells us if enable is true
or not).
En
I0
0 1 2 3 4 5 6 7
y0
0 1 2
y1
y2
I7
Eo
Gs
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Priority Encoder Implement a 32-input priority
encoder w/ 8 input priority encoders (high bit
priority).
En
y32, y31, y30
I31-24
Gs
Eo
y22, y21, y20
I25-16
Gs
Eo
y12, y11, y10
I15-8
Gs
Eo
y02, y01, y00
I7-0
Gs
Eo