Computer System Organization

1
Chapter 6

• Computer System Organization

2
Objectives

• We shall study computers as a collection of
  functional units or subsystems that perform tasks
  such as instruction processing, information
  storage, data transfer, input and output -
  Computer Organization
• All functional components are built from gates
  and circuits. However, those components will no
  longer be visible because we are going to be
  looking at these components at a higher level of
  abstraction.
• Most detailed view of a system - we can see all
  the components (each procedure)
• Grouping components - group related components
  together (e.g. procedures dealing with data
  parsing)
• Higher level of system - groupings are composed
  of systems (e.g. packages)
• Highest level - one component (e.g. application
  package)

3
Designing Computers

• All computers more or less based on the same
  basic design, the Von Neumann Architecture!

4
The Von Neumann Architecture

• Model for designing and building computers, based
  on the following three characteristics
• The computers four main sub-systems
• Memory
• ALU (Arithmetic/Logic Unit)
• Control Unit
• Input/Output System (I/O)
• Program is stored in memory during execution.
• Program instructions are executed sequentially.

5
The Von Neumann Architecture
Bus
Store data and program
Do arithmetic/logic operations requested by
program
6
Memory Subsystem

• Memory, also called RAM (Random Access Memory),
• Consists of many memory cells (storage units) of
  a fixed size. Each cell has an address
  associated with it 0, 1,
• All accesses to memory are to a specified
  address. A cell is the minimum unit of access
  (fetch/store a complete cell).
• The time it takes to fetch/store a cell is the
  same for all cells.
• When the computer is running, both
• Program
• Data (variables)
• are stored in the memory.

7
RAM
N

• Need to distinguish between
• the address of a memory cell and the content of a
  memory cell
• Memory width (W)
• How many bits is each memory cell, typically one
  byte (8 bits)
• Address width (N)
• How many bits used to represent each address,
  determines the maximum memory size address
  space
• If address width is N-bits, then address space is
  2N (0,1,...,2N-1)

0000 0000 0000 0001
1 bit
0
1
2
2N
2N-1
W
8
Memory Size / Speed

• Typical memory in a personal computer (PC)
• 64MB - 1GB
• Memory sizes
• Kilobyte (KB) 210 1,024 bytes 1 thou
• Megabyte(MB) 220 1,048,576 bytes 1 mil
• Gigabyte(GB) 230 1,073,741,824 bytes 1
  bil
• Memory Access Time (read from/ write to memory)
• 50-75 nanoseconds (1 nsec. 0.000000001 sec.)
• RAM is
• volatile (can only store when power is on)
• relatively expensive

9
Operations on Memory

• Fetch (address)
• Fetch a copy of the content of memory cell with
  the specified address.
• Non-destructive, copies value in memory cell.
• Store (address, value)
• Store the specified value into the memory cell
  specified by address.
• Destructive, overwrites the previous value of the
  memory cell.
• The memory system is interfaced via
• Memory Address Register (MAR)
• Memory Data Register (MDR)
• Fetch/Store signal

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Structure of the Memory Subsystem

• Fetch(address)
• Load address into MAR.
• Decode the address in MAR.
• Copy the content of memory cell with specified
  address into MDR.
• Store(address, value)
• Load the address into MAR.
• Load the value into MDR.
• Decode the address in MAR
• Copy the content of MDR into memory cell with the
  specified address.

F/S
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Memory Access
12
Memory Organization
address
0000
0001
0011
0010
0101
0111
0100
0110
1000
1001
1010
1011
1100
1101
1111
1110
Column selector lines
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CACHE Speeding Up Memory on the Cheap

• High-speed memory, Between the CPU and main
  memory
• c.10 times faster than RAM
• Relatively small (cf. main memory)
• Newer CPUs have several levels of cache,
  including some on-chip
• Stores data most recently used
• Principle of Locality of Reference
• When CPU needs data
• First looks in the cache, only if not there, then
  fetch from RAM.
• If cache full, new data overwrites older entries
  in cache.

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Example 1

• What is the dimension of a 2-d memory containing
  220 bytes of storage?
• How large would the MAR be?
• How many bits would be sent to the row and column
  decoders?
• How many output lines would the decoders have?

15
Example 2

• Assume the MAR has 12 select lines for the row
  and column decoders.
• What is the max size of the memory unit?
• What is the dimension of a 2-d memory
  organization?

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Input/Output Subsystem

• Handles devices that allow the computer system
  to
• Communicate and interact with the outside world
• Screen, keyboard, printer, ...
• Store information (mass-storage)
• Hard-drives, floppies, CD, tapes,
• Mass-Storage Device Access Methods
• Direct Access Storage Devices (DASDs)
• Hard-drives, floppy-disks, CD-ROMs, ...
• Sequential Access Storage Devices (SASDs)
• Tapes (for example, used as backup devices)

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I/O Subsystem Hard-Drives

• Uses magnetic surfaces to store the data.
• Each surface has many circular tracks.
• Each track consists of many sectors.

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Disk Access Time

• The time it takes to read/write data to a disk,
  consists of
• Seek time
• The time it takes to position the read/write head
  over correct track (depends on arm movement
  speed).
• Latency
• The time waiting for the beginning of the desired
  sector to get under the read/write head (depends
  on rotation speed)
• Transfer time
• The time needed for the sector to pass under the
  read/write head (depends on rotation speed and
  sector size)
• Disk Access Time Seek time Latency Transfer
  time
• Measure worst, best, and average case.

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I/O Controllers

• Speed of I/O devices is slow compared to RAM
• RAM 50 nsec.
• Hard-Drive 10 msec. (10,000,000 nsec)
• Solution
• I/O Controller, a special purpose processor
• Has a small memory buffer, and a control logic to
  control I/O device (e.g. move disk arm).
• Sends an interrupt signal to CPU when done
  read/write.
• Data transferred between RAM and memory buffer.
• Processor free to do something else while I/O
  controller reads/writes data from/to device into
  I/O buffer.

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Structure of the I/O Subsystem
Interrupt signal (to processor)
Data from/to memory
I/O device
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Example

• Number of sectors per track 50
• Number of tracks per surface 1000 (0 999)
• Number of surfaces 1
• Number of characters per sector 512
• Arm movement time 0.02 msec
• Rotation speed 7200 rev/min 120 rev/sec
  8.33 msec/rev

Number of Characters on the disk?
1 surfaces 1000 tracks 50 sectors 512 char
25 600 000
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Example

• Number of sectors per track 50
• Number of tracks per surface 1000 (0 999)
• Number of surfaces 1
• Number of characters per sector 512
• Arm movement time 0.02 msec/track
• Rotation speed 8.33 msec/rev

0.0
19.98
10.0
4.17
8.33
0.0
0.17
0.17
0.17
14.34
28.48
0.17
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The ALU Subsystem

• The ALU (Arithmetic/Logic Unit) performs
• mathematical operations (, -, x, /, )
• logic operations (and, or, not, ...)
• Is part of the CPU
• Consists of
• Circuits to do the arithmetic/logic operations.
• Registers (fast storage units, also known as the
  register scratchpad) to store intermediate
  computational results.
• Bus that connects the two.

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Structure of the ALU

• Registers
• Very fast local memory cells, that store operands
  of operations and intermediate results.
• CCR (condition code register), also known as the
  Flags register a special purpose register that
  stores the result of compare operations
• ALU circuitry
• Contains an array of circuits to do
  mathematical/logic operations.
• Bus
• Data path interconnecting the registers to the
  ALU circuitry.

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Implementation of the ALU

• Registers are similar to RAM except that
• registers are generally named and do not have
  numeric addresses
• registers can be accessed much more quickly than
  regular memory cells
• registers can be special purpose, e.g. data
  registers, address registers

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Implementation of the ALU
27
Implementation of the ALU
Every circuit produces a result but only the
desired one is selected
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The Control Unit

• Program is stored in memory
• as machine language instructions, in binary
• The task of the control unit is to execute
  programs by repeatedly stepping through the
  Information Processing Cycle
• Fetch from memory the next instruction to be
  executed.
• Decode it, that is, determine what is to be done.
• Execute it by issuing the appropriate signals to
  the ALU, memory, and I/O subsystems.
• Continues until the HALT instruction

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Structure of the Control Unit

• PC (Program Counter)
• stores the address of next instruction to fetch
• IR (Instruction Register)
• stores the instruction fetched from memory
• Instruction Decoder
• Decodes instruction and activates necessary
  circuitry

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Machine Language Instructions

• A machine language instruction consists of
• Operation (or order) code, telling which
  operation to perform
• Address field(s), telling the memory addresses of
  the values on which the operation works.
• Example ADD X, Y (Add content of memory
  locations X and Y, and store back in memory
  location Y).
• Assume opcode for ADD is 9, and addresses X99,
  Y100

Opcode (8 bits)
Address 1 (16 bits)
Address 2 (16 bits)
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Machine language instructions

• 4 Classes
• Data transfer operations that move information
  between or within the different components of the
  computer
• Arithmetic these are the operations that cause
  the ALU to perform a computation. Arithmetic
  operations (, -, , /), logical operations (AND,
  OR, NOT, XOR).
• Compare These are the operations that compare
  two values and set an indicator on the basis of
  the results of the compare. Most von Neumann
  machines have a special set of bits inside the
  processor called condition codes (also known as
  the flags register) and it is these bits that are
  set by the compare operations.
• Branch Alters the normal sequential flow of
  control. Enables the programming of loops.

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Instruction Set Design

• Two different approaches
• Reduced Instruction Set Computers (RISC)
• Instruction set as small and simple as possible.
• Minimizes amount of circuitry --gt faster
  computers
• Complex Instruction Set Computers (CISC)
• More instructions, many very complex
• Each instruction can do more work, but require
  more circuitry.
• Most contemporary machines are either pure RISC
  (e.g. Motorola PowerPC, MIPS, Sun SPARC) or have
  a RISC core inside a CISC architecture (Intel
  x86, AMD Athlon)

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Typical Machine Instructions

• Notation
• We use X, Y, Z to denote RAM cells
• Assume only one register R (for simplicity)
• Use English-like descriptions (should be binary)
• Data Transfer Instructions
• LOAD X Load content of memory location X to R
• STORE X Load content of R to memory location X
• MOVE X, Y Copy content of memory location X
  to location Y (not absolutely necessary
  why?)

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Machine Instructions (cont.)

• Arithmetic
• ADD X, Y, Z gt CON(Z) CON(X) CON(Y)
• ADD X, Y gt CON(Y) CON(X) CON(Y)
• ADD X gt R CON(X) R
• similar instructions for other operators, e.g.
  SUB,OR, ...
• Compare
• COMPARE X, YCompare the content of memory cell X
  to the content of memory cell Y and set the
  condition codes (CCR) accordingly.
• E.g. if CON(X) CON(Y) EQ1, GT0,
  LT0

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Machine Instructions (cont.)

• Branch
• JUMP X Load next instruction from memory loc.
  X
• JUMPGT X Load next instruction from memory
  loc. X only if GT flag in CCR is
  set otherwise load statement from next
  sequential loc. as usual.
• Also
• JUMPEQ
• JUMPLT
• JUMPGE
• JUMPLE
• JUMPNEQ
• Control
• HALT Stop program execution.

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Example

• Pseudo-code A B C
• Assuming variable
• A stored in memory cell 100
• B stored in memory cell 150
• C stored in memory cell 151
• Machine language (really in binary)
• LOAD 150
• ADD 151
• STORE 100

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Example 2

• Pseudo-code a bcd
• LOAD b
• ADD c
• ADD d
• STORE a

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Example 3

• Pseudo-code a d while a lt
  c a ab

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Implementation of the Control Unit
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Organization of a von Neumann Computer
Not von Neumann
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How does this all work together?

• Program Execution
• PC address of first instruction in memory
• halting FALSE
• while not halting
• IR fetch (PC) get next instruction
• PC PC 1 point PC to one after that
• decode (IR) what kind of instruction?
• execute (IR) do it could set halting TRUE

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Program Execution (cont.)

• Fetch phase
• PC --gt MAR (put address in PC into MAR)
• Fetch signal (signal memory to fetch value into
  MDR)
• MDR --gt IR (move value to Instruction Register)
• PC 1 --gt PC (Increase address in program
  counter)
• Decode Phase
• IR --gt Instruction decoder (decode instruction in
  IR)
• Instruction decoder will then generate the
  signals to activate the circuitry to carry out
  the instruction
• Execute Phase
• Differs from one instruction to the next.

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Example

• LOAD X (load contents of address X to R register)
• IRaddr --gt MAR move operand address to MAR
• Fetch signal issue a memory fetch signal
• MDR --gt R copy MDR to R register
• ADD X (add contents of address X to R register)
• IRaddr --gt MAR move operand address to
  MAR Fetch issue a memory
  fetch signal MDR --gt ALUin1 send the
  two operands of the R --gt ALUin2
  ADD to the ALU
• ADD activate the ALU
  and select the output of the add
  circuit ALUout --gt R copy the ALU
  output into the R register

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Instruction Set
45
Von Neumann Machine Operation

• Given this machine code and the memory location,
  how would the fetch-decode-execute cycle work?
• Memory Address Content Operation
• 000 0000000000000101 load x
• 001 0011000000000110 add y
• 010 0001000000000111 store z
• 011 1110000000000111 out z
• 100 1111000000000000 halt
• 101 0000000000000010 x data 2
• 110 0000000000000100 y data 4
• 111 0000000000000110 z data 0

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Fetch Phase 1
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Execute Phase 1
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Fetch Phase 2
49
Execute Phase 2
50
Fetch Phase 3
51
Execute Phase 3
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Fetch Phase 4
53
Execute Phase 4
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Fetch Phase 5
55
Execute Phase 5