Task III: Novel Communications Mechanisms

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Task III Novel Communications Mechanisms
Task Leaders L. C. Kimerling, MIT and D. A. B.
Miller, Stanford
Other principal investigators M. F. Chang,
UCLA E. A. Fitzgerald, MIT C. G.Fonstad, MIT J.
S. Harris, Stanford P. Persans, RPI
Optical and RF technologies for on-chip and
off-chip interconnection and clock distribution
to provide a scalable platform for bandwidth,
signal integrity and synchronization.
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Objectives RF and optical interconnection for
chip and MCM/PWB interconnection. Interconnectio
n design and performance does not scale with
technology shrink. Speed, crosstalk and power
dissipation metrics degrade.Optics offers a
scalable solution for all levels of the
interconnection hierarchy. The Task 3 team
includes materials, processing and device experts
in silicon/germanium, compound semiconductors,
and dielectrics.The projects within the Task
cover applications of these systems to hybrid and
monolithic fabrication approaches to best assess
the value of optical interconnection.Many of our
interfaces with the other Centers are through
projects with other Tasks (architecture and
design).
Approaches Prototype hybrid and monolithic
architectural platforms for IFC
Drivers. Technical analysis (w/Task 1,2) of
RF/optical interconnection with design criteria
for speed/power/area tradeoff. Evaluation of
novel architectures free space and optical bus
prototypes (w/Tasks 1,2) for chip I/O and clock
distribution IFC Drivers. Develop CAD tools
for device design, component integration and
partitioning of optics/electronics (w/Tasks
2,6). Develop materials and processes for
integration on silicon (w/Task 5). Assess the
limits of scalability of performance and
integration. Develop entry-level functionality
for receivers, synchronization and MCMs (w Task
4).
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THE ECONOMICS OF INTEGRATION
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Technology Evolution
Integration
102 cm2
Scaling
10-4 cm2
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Microphotonics Large Scale Integration

• Photonic functionality
• Clock, I/O, Signal Processing
• High yield, low cost
• Monolithic
• High bandwidth
• Optical carrier
• Reduced interconnection density
• WDM
• Figure-of-Merit speed/(power x area)

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MONOLITHIC SILICON MICROPHOTONICS
Kimerling Group, MIT
APPROACH To create technology building blocks
under the constraints of the conventional silicon
fabline, IC design and systems performance
requirements.

• MILESTONES
• Low loss Si nanowaveguides
• Integrated SiEr LED / CMOS driver
• Microresonator devices and circuits
• 16x fanout clock signal
• Vertically coupled architectures
• Ge on Si photodetectors
• Wafer bonded isolation/integration

V
R770 mA/W with AR Coating
t 280pS (100x100mm)
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Optical Clock Distribution Tasks I, II, III

• Approach
• off-chip optical source
• distribute by waveguides
• optoelectronic conversion detector and
  reciever circuit
• local electrical clock distribution
• Potential Advantages
• low skew distribution of optical signals,
  thus very high speed clocking
• low noise
• power reduction

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COMPONENTS FOR OPTICAL INTERCONNECTION
Si/SiO2 Waveguides (Dn2) small dimensions low
cross-talk small radius bend multi-level
interconnection Ge Photodetectors Si process
compatibility l 1.3-1.55mm performance indirec
t bandgap 4 lattice mismatch

• Key issues
• equal power distribution
• integrated coupling from waveguide to detector
• high detector responsity due to multiple
  H-tree/fan-out
• small waveguide bend radius
• CMOS compatibility

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The Scaling Law Index Contrast
2001
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Silicon Waveguide Bends
Fabricated at Intel Corp.
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CMOS-compatible optical waveguides
Principal investigator Peter Persans, Rensselaer
Goal develop and evaluate materials and
processes to enable fabrication of optical
waveguides and couplers for on-chip, chip to
chip, and 3D chip architectures

• Important tasks
• Design new optical beam steering structures based
  on materials properties and optical beam
  propagation modeling
• Develop and model CMOS-compatible processes
• Characterize new materials properties (loss,
  stability)
• Fabricate and test materials and structures for
  multi-scale applications

• Example of waveguide implementation
• coupling from chip to chip with optics in an
  interconnect sub- or super- strate

chip
substrate, w/metal and optical interconnects

• lateral dimensions 1-10?m
• length 20 mm

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surface and sidewall roughness during RIE etching

• top surface roughness increases with etch depth
• O2/HCF3 plasma etching

• high pressure plasma leads to smoother top surface

40 mT
gt500 mT

• dependence of loss on guide width show loss is
  due to sidewall scattering
• sidewall roughness is lower for lower pressure RIE

• roughness w?d
• scaling exponent ?1
• correlation length 0.4 ?m

(Agarwal et al., App. Phys. Lett., 78 (2001)
modeling with T. Cale)
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Dislocation free, direct Ge on Si Photodetectors
Ge
SiO2
SiO2
SiO2
Si
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Si Microphotonic I/O
Si Waveguide
WDM Add/Drop
Ge Photodetector
1530 nm
1530 nm 1540 nm 1550 nm 1560 nm 1570 nm .
1540 nm
1570 nm
1550 nm
1560 nm
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Silicon Racetrack Response
Silicon
Silica
6 um
Drop
In
Fabricated with P. Maki at MIT Lincoln Labs
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Q vs. Radius

• Q dependence on R
• Increased coupling length
• Longer path length, Qe
• Scattering, Ql

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Q vs.Gap

• Q dependence on Gap
• Increased Gap reduces coupling.
• Increases Qe.

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1x4 WDM in Silicon Nitride
Efficiency 100, Q500 Co-Workers B. E. Little
, H. A. Haus, MIT Devices fabricated at MIT
Lincoln Labs with Paul Maki
Thru-port
Thru-port
1
2
3
4
19

• Vertical coupling allows precise control of
  resonator Q
• Racetracks enable better coupling
• Trimming and tuning may be necessary

D.R. Lim
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Proven Si/SiGe/GaAs Integration
Fitzgerald Group, MIT

• Low Defect Density Relaxed SiGe/Si Substrates
• TDD lt 1x106 cm-2
• S. B. Samavedam, M. T. Currie, T. A. Langdo, C.
  W. Leitz, E.A. Fitzgerald
• III-V on IV Growth
• MOCVD and MBE growth of low-defect GaAs diodes
• S.M. Ting, J.A. Carlin, S.Ringel,E. Fitzgerald

GaAs
Ge
SiGe
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True Monolithic Integration of GaAs on Si

• I-V characteristics excellent
• Minority carrier lifetimes nearly equivalent
• Solar cells equivalent
• Bi-directional monolithic optical links on
  GaAs/Si,
• Yang et al.
• CW Room T AlGaAs/GaAs lasers on Ge/SiGe/Si
• Groenert et al.

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Room Temp. CW Laser on Si

• GaAs/AlGaAs QW laser on Ge/SiGe/Si operates cw at
  ? 858nm
• Comparable performance to identical device on
  GaAs substrate

First monolithically integrated laser on Ge/GeSi
virtual substrate on Si!
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Monolithically Integrated Mode-locked VCSEL

• New concept for short pulse laser
• Passively mode-locked VCSEL using fast saturable
  absorber.
• Substrate used as long cavity.
• Spherical mirror design for stable resonator.
• 980nm gain region, saturable absorber
• and planar mirror grown by MBE.
• Subpicosecond pulses and tens of GHz
• repetition rates expected.
• Potential Applications
• Optical clock distribution
• Short-pulse interconnect
• WDM interconnect.

Rafael I. Aldaz, James S. Harris, Jr., Stanford
University
AFM image of 60um diameter spherical surface
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GaInNAs Long Wavelength Lasers
GaInNAs cw VCSEL

• Applications
• Low power optical interconnects
• Direct connection to telecommunications
  wavelengths
• Low cost, directly modulated 1.3-1.55 µm VCSELs
• Approach
• Investigate metastable growth and annealing
• of GaInNAs grown by N plasma MBE
• Accomplishments
• Demonstrated first cw, room temperature
• GaInNAs VCSEL at 1.22µm
• Developed novel GaNAs barrier, GaInNAs
• quantum well structure for gt1.3µm lasers
• Developed optimum annealing to achieve
• low threshold current lasers at 1.3-1.4µm
• Extended PL to 1.6µm and laser to 1.48µm
• by addition of Sb GaInNAs(Sb)

GaInNAs(Sb) laser
J. S. Harris, Stanford
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Flip-Chip Bonding of GaAs devices to Silicon CMOS
Solder-bonded quantum well modulators and
detectors bonded in arrays of 200 on silicon CMOS
chips on 62.5 x 125 micron pitch
Miller Group, Stanford

• Several different functioning chips successfully
  bonded and used in working chip interconnect
  demonstrations
• WDM interconnect chip (0.5 micron), OPTLAT
  latency test chip (0.25 micron), Clocked receiver
  chip (collaboration with Mark Horowitz)

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O/E/O Latency Reduction using Short Optical Pulses
Miller Group, Stanford

• Measured O/E/O latency with picosecond resolution
• Significant latency improvement using short
  pulses (vs. NRZ)
• Also demonstrated receiver sensitivity
  enhancement with short pulses

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Integration of InP-based Photodetectors with
Si-CMOS for Clock Distribution Wojciech
Giziewicz, Clifton G. Fonstad, MIT
Concept Optical solder bumps for chip I/O and
clock distribution Features Modular
and monolithic wafer-scale, batch
processing Commercial foundry ICs and
heterostructures Initial implementation using
Aligned Pillar Bonding (APB) Immediate goal
APB-integrate and characterize high-speed 1550
nm photodetectors on CMOS chips designed by
Boning et al evaluate optical clock distribution
concepts
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Optical Solder Bumps photodetector/receiver
circuit
MARCO Review - 1/7/02
Professor Clifton G. Fonstad
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The EDFA vs. an Er2O3 Waveguide Amplifier

• Microphotonics higher gain/cm
• ErEr2O3 1?1022 cm-3 ?
  300 dB/cm
• ErEDFA 1?1017-1019cm-3 ?
  0.0002-0.06 dB/cm
• Gain limiting effects energy migration,
  upconversion

2 H 11/2
E
4 I 9/2
4 I 11/2
4 I 13/2
0.56 mm
4 I 15/2
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High Gain Prospects

• N gt 1020 cm-3, upconversion rate ?
• limit gain efficiency (dB/mW)
• Upconversion rate limitation
• number of Er atoms
• not Er atom-atom distance

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SCHEDULE OF ANTICIPATED MILESTONES

• Determination of speed/power/crosstalk/footprint
  tradeoffs
• for each IFC driver application and assess the
  limits of scalability
• of performance and integration. (w Task 1 next
  4Q).
• 2. Demonstration of GHz clock and Gb/s I/O
  distribution functions.
• (w Task 2 next 8Q with emphasis on receiver
  circuits, insertion loss
• and signal distribution).
• Develop CAD tools for device design, component
  integration and
• partitioning of optics/electronics (w Tasks 2,6
  next 4Q).
• Design stabilized prototypes for early entry
  applications of optics
• such as testing and MCM/PWB functions (w Task 4
  future).
• Develop materials and processes for monolithic
  integration on silicon
• (w Task 5 next 4Q).

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A key area for expansion in interconnects is a
potential redisign of the entire interconnection
hierarchy, from chips to networks.In particular,
there is good reason to believe that photons can
be routed directly to the chip without
intervening levels.Since photonics does not rely
on wire diameter to scale with distance as does
electronics,a single interface could be
sufficient.The payoff is significant
simplification of systems.