A comprehensive survey of aging issues on digital circuits

1
A comprehensive survey of aging issues on digital
circuits

• Cheng-Han Sung
• Meng Shi
• Prof. Saluja

2
Outline

• Motivation
• Aging Effect on Transistors
• Aging Effect on Interconnects
• Conclusion

3
Motivation

• As the feature size of transistors shrinks,
  transistors and interconnects become more
  sensitive to aging effect, and thus reliability
  becomes an issue
• Hence, how to design circuits which can tolerate
  aging effects is an design challenge

4
Aging Effect on Transistors

• Fundamental of MOS transistors
• Negative Bias Temperature Instability
• Channel Hot Carrier
• Proposed approaches

5
Fundamental of MOS transistors

• Due to the simplicity and fair cost, MOSFETs have
  been widely used in IC industry

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Fundamental of MOS transistors

• As the feature size of transistors shrinks,
  supply voltage decreases due to hot electron
  effect
• This supply voltage reduction results in the
  insufficient amount of accumulated carrier in
  channel, that is, this transistor can not be
  fully on

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Fundamental of MOS transistors

• To fix this problem, we could either reduce
  thickness of gate oxide or use high k material, a
  material with high dielectric constant
• The former leads to a serious gate leakage
  current problem. Therefore, semiconductor
  engineers are adopting the latter

8
Fundamental of MOS transistors

• For the simplicity of fabrication process and
  improvement of reliability, polysilicon gate, one
  kind of self-aligned techniques, is adopted in
  fabrication process
• Some research have indicated that p type (i.e.
  Boron) polysilicon gate has a better performance
  than that of n type polysilicon gate. Therefore,
  p type polysilicon gate is now adopted in
  industry instead of medal gate
• However, boron penetration occurs and leads to
  instability of threshold voltage of PMOS

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Negative Bias Temperature Instability (NBTI)

• In the advanced semiconductor technologies,
  Nitrogen is introduced into gate oxide (i.e.
  silicon nitride) as high k material and to
  prevent boron penetration

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Negative Bias Temperature Instability (NBTI)

• Based on Reaction-Diffusion (RD) model,
  accumulated holes could interact with hydrogen
  passivated with silicon and break Si-H bonds,
  thus creating dangling bonds, and the introduced
  Nitrogen accelerate this process

K. Kang et al., NBTI Induced Performance
Degradation in Logic and Memory Circuits How
Effectively can we Approach a Reliability
Solution? in Proc. ASPDAC, pp. 726731, 2008
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Negative Bias Temperature Instability (NBTI)

• These dangling bonds behaves like interface
  traps, which interfere free carriers (i.e. free
  holes) in channel by trapping and releasing
  mechanism
• Its effect is equivalent to the increase of
  threshold voltage
• Currently, NBTI is only observed in PMOS, while
  PBTI is not obvious in NMOS

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Channel Hot Carrier (CHC)

• As mentioned previously, supply voltage is
  reduced due to hot carrier effect, which results
  from a high horizontal electric field
• However, free carriers could hit the interface
  hardly and be trapped there due to a strong
  vertical electric field

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Channel Hot Carrier (CHC)

• Because of the trapped charges on interface, the
  applied gate voltage could not attract enough
  free carriers to form a channel, that is, this
  transistor can not be fully on
• Its effect is also equivalent to the increase of
  threshold voltage
• CHC phenomenon can be observed in both NMOS and
  PMOS

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Proposed approaches

• Since the effect of mentioned aging issues is
  equivalent to the decrease of drain current,
  performance compensation might be achieved by
  changing parameters in drain saturation current
  equation
• Gate sizing
• Multi-supply voltage
• Forward Body Bias

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Proposed approaches

• The nature of gate sizing approach is over
  design. By estimating the worst delay due to
  aging effects, the size of logic gates are
  enlarged, such that circuits can meet timing
  requirement in the worst case scenario
• This approach trades reliability with area
  overhead due to over design
• Usually, Linear Programming (LP) is adopted to
  achieve performance requirement while extra cost
  is minimized

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Proposed approaches

• It is straight forward to provide different
  supply voltages to transistors with different
  extent of aging effect.
• However, it is impractical to provide each of
  millions of transistors an individual supply
  voltage
• Since our goal is to sustain system performance,
  we can divide chips into a finite number of areas
  and provide individual supply voltages for each
  of them

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Proposed approaches

• Forward body bias manifests itself as the
  decrease of threshold voltage. One common
  empirical model is shown as
• Increasing body voltage of NMOS results in the
  decrease of threshold voltage, while decreasing
  body voltage of PMOS results in the decrease of
  threshold voltage

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Proposed approaches

• Once we determine what factor we want to change
  in run time, we need to know what value we should
  provide to circuit. Otherwise, self-reconfiguratio
  n is not doable
• Look up table based approach
• The replica of critical path based approach
• Model based estimation approach

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Proposed approaches

• In look up table approach, chips with aging
  effect are tested by tester, delay are measured
  for different factor values (i.e. different
  supply voltages), and the factor value with the
  best performance are saved in look up table. The
  same procedure are applied to chips with
  different aging effect
• This approach, however, requires a significant
  amount of silicon area. Therefore, the replica of
  critical path approach was proposed

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Proposed approaches

• In the replica of critical path approach, the
  replica of critical path is implemented in chips
• By measuring the delay of critical path, we can
  acquire more accurate information and make a
  better choice of factor value, and also save a
  significant amount of silicon area

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Proposed approaches

• Among many different models for NBTI effect,
  Reaction-Diffusion model is the one which is
  closest to the observations for NBTI
• where delay Nit represents the interface trap
  density, Kf and Kr are bond break and annealing
  rate, respectively, N0 is the maximum silicon
  density, DH is diffusion coefficient, and t
  represents time

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Proposed approaches

• The resulting threshold voltage deviation is
  shown as
• By the given threshold voltage deviation, the
  delay and deviation ratio of logic gate can be
  expressed as

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Proposed approaches

• To substitute threshold voltage deviation by Atn
  (i.e. n0.25) and take logarithm on both sides,
  we can get
• Similarly, the same idea can be used to estimate
  circuit delay, and it is shown as

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Aging effect on Interconnects

• Structure of Interconnects
• What is Electromigration?
• Factors Affect Electromigration
• MTTF of Electric Interconnects
• Approaches to Mitigate Electromigration

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Structure of Interconnects

• Aluminum and Copper interconnects are
  polycrystalline and consist of grains (single
  crystals)
• Perfect lattice no resistance -gt no interaction
  between
• the moving
  electrons and the metal atoms
• No perfect lattice exists above absolute zero
• atom vibration
• impurity
• boundaries of crystal lattice having different
  orientations
• Interactions between the electrons and the metal
  atoms exist as current flows through wire

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What is Electromigration?

• Electromigration is the mass transport of a metal
  due to momentum exchange between conducting
  electrons and diffusing metal atoms
• Momentum Exchange is the force due to collisions
  of electrons to metal atoms
• Collisions produce a force on the metal atoms in
  the direction of electron flow

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Forces on Metal Atoms

• Current flowing through a conductor produces two
  forces to individual metal atom
• - electrostatic force
• - caused by the electric field strength
• - can be ignored in most cases
• - generated by the momentum transfer
• - in the direction of the electron flow
• - main cause of electromigration

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Forces on Metal Atoms

• Electromigration is the result of the dominant
  force -- the momentum transfer from the electrons
  which moves in the applied electric field

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Asymmetry in Crystal Structure

• The atoms on the crystal boundaries are bounded
  more weakly than inside the lattice
• Asymmetry structure on grain boundaries and
  material interfaces leads to vigorous momentum
  transfer
• In appearance of current flow, metal atoms at the
  grain boundaries especially will fall victims to
  move in the direction of electron wind

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Voids and Hillocks

• Hillocks accumulation of moving metal atoms in
  some individual grain boundaries in the direction
  of the electron flow
• Voids appear at the grain boundaries where those
  moving atoms belonged before they got enough
  energy to move

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Voids and Hillocks

• Voids will finally result in open circuit that
  can cause functional failure of the circuit
• Hillocks will result in short circuit between
  adjacent interconnects

1 mil wide AL stripe I/C conductor fails due to
electromigration
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Factors Affect Electromigration

• The flux of atoms
• the mobility of the moving atoms
• the force acting on the moving atoms
• Apply Einstein relation
• diffusing coefficient of moving atoms
• absolute temperature
• Boltzmann constant

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Factors Affect Electromigration

• In case of electromigration
• effective charge on the moving atoms
• electric field,
• resistivity of the conductor
• current density

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Factors Affect Electromigration

• Electromigration occurs at the sites where atomic
  flux diverges
• Electromigration-induced mass flux is directly
  proportional to the current density, the
  diffusion coefficient, concentration of diffusing
  atoms

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Factors Affect Electromigration
-- Current Density

• Appearance of Voids
• cross sectional area ?
• current flow ?
• local current density ?
• local resistance ?
• gt electromigration effects ?
• History of electromigration

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Factors Affect Electromigration -- Temperature
Diffusion Coefficient

• The major effect of temperature on
  electromigration is on diffusion coefficient
• Diffusion coefficient
• D is exponentially dependent on temperature
• Increase temperature
• gt increase diffusivity
• gt increase electromigration

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Factors Affect Electromigration
-- Temperature Gradients

• A portion of the conductor is at a higher
  temperature than the rest part of the conductor
• Voids form between the cold and hot zones
• Hillocks form between the hot and cold zones

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Factors Affect Electromigration
-- Grain Structure Gradients

• Change of grain size will cause flux divergence
• flux(right) gt flux(left) --more grain boundaries
  to support mass transport for the left to right
  electron current
• voids would form near the middle of this structure

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MTTF of Interconnects

• A cross-section area
• J current density
• Ea activation energy
• K Boltzmann constant
• T temperature
• n scaling factor
• J and T are the deciding factors of
  electromigration process

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Approaches to Mitigate Electromigration

• Minimize Current Density
• - avoid highly integrated circuits with
  extremely small active-device areas
• Optimize metallization processing parameters
• - increase grain size
• Increase electromigration activation energy Ea
• - alloy Aluminum with little Copper or
  silicon
• Encapsulate
• - depositing a layer of SiO2 or glass on top
  of the metallization to reduce surface migration

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Conclusion

• Electromigration is closely related to the
  reliability of integrated circuit
• In order to mitigate electromigration, flux
  divergence need to be minimized and can be
  achieved by decreasing current density,
  stabilizing temperature, and enlarging grain size

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Thank you!