Functional Test Program Generation for Microprocessors

1
Functional Test Program Generation for
Microprocessors

• Prabhat Mishra

2
Outline

• Introduction
• Test Program Generation Taxonomy
• Test Program Generation Techniques
• Past Approaches
• Present Trends
• Future Directions
• Conclusion
• References

3
Introduction

• Shrinking time-to-market, short product life ..
• Need to reduce design cycle time for embedded
  microprocessors.
• Functional verification is one of the major
  component of this design cycle time.
• Existing validation approaches
• Simulation based approaches using random tests
• Formal techniques to verify certain properties

4
Test Generation Taxonomy
Test Generation
Functional Test
Manufacturing Test
Verifies Functional Correctness
Verifies stuck-at, bridging, delay.. faults
5
Test Generation Taxonomy
Test Generation
Functional Test
Manufacturing Test
Fault Oriented
Fault Independent
Random
Combined
(RAPS, SMART)
(Critical Path)
6
Test Generation Taxonomy
Test Generation
Functional Test
Manufacturing Test
Implicit (universal) Fault
Without Fault
Functional Fault
Fault Oriented
Fault Independent
Random
Combined
7
Test Generation Taxonomy
Test Generation
Functional Test
Manufacturing Test
Implicit (universal) Fault
Without Fault
Functional Fault
Fault Oriented
Fault Independent
Random
Combined
BDD
Heuristic
8
Test Generation Taxonomy
Test Generation
Functional Test
Manufacturing Test
Implicit (universal) Fault
Without Fault
Functional Fault
Fault Oriented
Fault Independent
Random
Combined
PseudoExhaustive
Exhaustive
BDD
Heuristic
9
Test Generation Taxonomy
Test Generation
Functional Test
Manufacturing Test
Implicit (universal) Fault
Without Fault
Functional Fault
Fault Oriented
Fault Independent
Random
Combined
PseudoExhaustive
Exhaustive
BDD
Heuristic
10
Test Generation Taxonomy
Test Generation
Functional Test
Manufacturing Test
Implicit (universal) Fault
Without Fault
Functional Fault
Fault Oriented
Fault Independent
Random
Combined
PseudoExhaustive
Exhaustive
BDD
Heuristic
11
Functional Test Program
TestProgGen
MOV R1, 011 MOV R2, 010 ADD R3, R1, R2 R3 101
R3 101 ?
Verifies the functionality of the processor using
assembly programs
12
Test Program Generation Techniques

• Past Approaches
• Functional Fault Model based Test Generation
• Present Trends
• Micro-Architecture Coverage driven Test Gen.
• Instruction-Level Self Test
• Specification based Test Generation
• Future Directions
• Software based Self Test
• Specification driven Validation

13
Test Program Generation Techniques

• Past Approaches
• Functional Fault Model based Test Generation
• Nair et. al., IEEE Computers 1978
• Thatte et al. IEEE Computers,1980
• Brahme et al. IEEE Computers,1984
• Lin et al., DAC 1988
• Kannah et al., ATS 2000
• Present Trends
• Micro-Architecture Coverage driven Test Gen.
• Instruction-Level Self Test
• Specification based Test Generation
• Future Directions
• Software based Self Test
• Specification driven Validation

14
Testing Random-Access Memories

• Presented a fault model which views faults in
  memories at a functional level instead of at a
  basic gate level.
• Memory Fault Model
• Memory cell array
• One or more cells are stuck at 0 or 1.
• One or more pairs of cells are coupled.
• Decoder
• Does not access the addressed cell
• Access multiple cells, including the addressed
  cell
• Read/Write Logic
• Some output lines of the sense amplifier logic or
  write driver logic may be stuck-at-0 or
  stuck-at-1

Nair et. al., IEEE Computers 1978
15
Testing of Microprocessors

• Graph model of the architecture
• Node Register groups
• Edge Instructions
• Functional fault models
• Register decoding
• Instruction decoding
• Data Storage
• Data Transfer
• Data Manipulation
• Test generation procedure
• Register decoding

Thatte et. al., IEEE Computers 1980
16
Graph Model of the Microprocessor
Registers R1 accumulator R2
general purpose register R3 scratch-pad register
In
I2
I1
I3
I7
Instructions I1 Load R1 I2 Load R2 I3
Add R1 R1 R2 I4 Mov R2 R1 I5 Store R1 I6
Store R2 I7 Mov R3 R1 I8 Mov R1 R3
I4
R2
R1
R3
I3
I8
I6
I5
Out
17
Graph Model of the Microprocessor
Registers R1 accumulator R2
general purpose register R3 scratch-pad register
Instructions I1 Load R1 I2 Load R2 I3
Add R1 R1 R2 I4 Mov R2 R1 I5 Store R1 I6
Store R2 I7 Mov R3 R1 I8 Mov R1 R3
Write (R3) I1, I7 Read(R3) I8, I5
18
Microprocessor Fault Models

• Register Decoding
• fd(Ri) Ri
• Write (Ri) and Read (Ri)
• Instruction Decoding
• No instruction executed f (Ij / )
• Different instruction is executed f(Ij / Ik )
• F(Ij / Ij Ik )
• Data Storage
• Any cell of a register can be stuck-at-0 or
  stuck-at-1
• Data Transfer
• A line in a transfer path can be stuck at 0 or 1
• Two lines in a transfer path can be coupled
• Data Manipulation

19
Test Generation for Register Decoding

• Initialize Q with all registers so that Ri lies
  ahead of Rj iff l(Ri) lt l(Rj)
• A register at the front of the Q
• Repeat
• Write each register Ri of set A with data ONE and
  register Rj at the front of Q with data ZERO
• Read each register Ri of A
• Read Rj
• A A U Rj
• Q Q - Rj
• Until Q is empty

f(Ri) ? ?, for every Ri ? A f(Ri) ? f(Rj) ? for
every Ri, Rj ? A ??f(Ri)? 1
20
Register Decoding Algorithm
A Q R1, R2, R3
21
Register Decoding Algorithm
A Q R1, R2, R3
R1 ? ZERO R1 ? ZERO ?
LOAD R1, ZERO STORE R1 Out ZERO ?
22
Register Decoding Algorithm
A Q R1, R2, R3 A R1 Q R2, R3
R1 ? ZERO R1 ? ZERO ?
23
Register Decoding Algorithm
A Q R1, R2, R3 A R1 Q R2, R3
R1 ? ZERO R1 ? ZERO ? R1 ? ONE, R2 ? ZERO R1 ?
ONE ?, R2 ? ZERO ?
24
Register Decoding Algorithm
A Q R1, R2, R3 A R1 Q R2, R3 A
R1, R2 Q R3
R1 ? ZERO R1 ? ZERO ? R1 ? ONE, R2 ? ZERO R1 ?
ONE ?, R2 ? ZERO ?
25
Register Decoding Algorithm
A Q R1, R2, R3 A R1 Q R2, R3 A
R1, R2 Q R3
R1 ? ZERO R1 ? ZERO ? R1 ? ONE, R2 ? ZERO R1 ?
ONE ?, R2 ? ZERO ? (R1, R2) ? ONE, R3 ?
ZERO (R1, R2) ? ONE ?, R2 ? ZERO ?
26
Register Decoding Algorithm
A Q R1, R2, R3 A R1 Q R2, R3 A
R1, R2 Q R3 A R1, R2, R3 Q
R1 ? ZERO R1 ? ZERO ? R1 ? ONE, R2 ? ZERO R1 ?
ONE ?, R2 ? ZERO ? (R1, R2) ? ONE, R3 ?
ZERO (R1, R2) ? ONE ?, R2 ? ZERO ?
27
Extended Fault Model

• Representation for Instructions
• An instruction is composed of a sequence of
  microinstructions.
• Each microinstruction is made up of a set of
  microorders which are executed in parallel
• SWAP, CLR, NOT, MOV, EXG, ADD, MUL, DIV
• Simple ADD has 4 microorders
• Fault model for the Instruction Sequencing
• One or more microorders can be inactive
• Microorders which are normally inactive become
  active
• F(I) I - -

Brahme et. al., IEEE Computers 1984
28
Further Improvements

• Chen-Shang Lin and Hong-Fa Ho, DAC 88
• Signal flow model of the processor
• Functional fault models are derived from Turing
  machine model
• Developed O-algorithm to eliminate redundant
  tests and obtain improved fault coverage
• Rajesh Kannah, C.P. Ravikumar, ATS 2000
• Reduce the test application time.
• Use structural information to eliminate certain
  functional tests using the notion of
  fault-grading.

29
Test Program Generation Techniques

• Past Approaches
• Functional Fault Model based Test Generation
• Present Trends
• Micro-Architecture Coverage driven Test
  Generation
• Iwashita et al., ICCAD 1994
• Ho et al., ISCA 1995
• Ur et al., DAC 1999
• Campenhout et al., DAC 1999
• Specification driven Test Generation
• Geist et al., DAC 1999 (Specman Elite from
  Verisity)
• Mishra et al., HLDVT 2002
• Instruction-Level Self Test
• Lai et al., DAC 2001
• Chen et al., DAC 2003
• Future Directions
• Software based Self Test
• Specification driven Validation

30
Test Generation for Pipelined Processors
Iwashita et. al., ICCAD 1994
31
FSM Traversal based Test Generation
Ho et. al., ISCA 1995
32
Micro Architecture Coverage Driven
Ur et. al., DAC 1999
33
High-Level Test Generation
Campenhout et. al., DAC 1999
DPTRACE Path Selection DPRELAX Value
Selection CTRLJUST Signal Justification
34
Test Program Generation Techniques

• Past Approaches
• Functional Fault Model based Test Generation
• Present Trends
• Micro-Architecture Coverage driven Test
  Generation
• Iwashita et al., ICCAD 1994
• Ho et al., ISCA 1995
• Ur et al., DAC 1999
• Campenhout et al., DAC 1999
• Instruction-Level Self Test
• Lai et al., DAC 2001
• Chen et al., DAC 2003
• Specification driven Test Generation
• Geist et al., DAC 1999 (Specman Elite from
  Verisity)
• Mishra et al., HLDVT 2002
• Future Directions
• Software based Self Test
• Specification driven Validation

35
Specman Elite from Verisity Inc.
36
Specification driven Test Gen. using Model Checker
Architecture Specification
ADL Specification
Properties (SMV)
Processor Model
Simulator Generation
Not Enough Properties
SMV
Counterexamples
Coverage Report
Simulator
Automatic
Test Programs
Manual
Mishra et. al., HLDVT 2002
37
Test Program Generation

• Specification of Properties
• Stall Decode Unit of the DLX architecture
• stall assert G(ID._stall 0)
• Test Program
• The Decode unit (ID) will be stalled in cycle 4.

Fetch Cycle Opcode Dest Src1 Src2
1 NOP 2 ADD
R3 R1 R2 3
ADD R4 R3 R2
38
Test Program Generation Techniques

• Past Approaches
• Functional Fault Model based Test Generation
• Present Trends
• Micro-Architecture Coverage driven Test
  Generation
• Iwashita et al., ICCAD 1994
• Ho et al., ISCA 1995
• Ur et al., DAC 1999
• Campenhout et al., DAC 1999
• Specification driven Test Generation
• Geist et al., DAC 1999 (Specman Elite from
  Verisity)
• Mishra et al., HLDVT 2002
• Instruction-Level Self Test
• Lai et al., DAC 2001
• Chen et al., DAC 2003
• Future Directions
• Software based Self Test
• Specification driven Validation

39
Instruction-Level DFT
Lai et. al., DAC 2001
40
Software-Based Self-Test
Chen et. al., DAC 2003
41
Conclusion

• The boundary is blurring ..
• Confluence of Functional Verification and
  Manufacturing testing
• Software-Based Self-Test
• Top-down and Bottom-up Validation
• Specification driven Test Generation
• Micro-Architecture Coverage driven Techniques
• Combined Simulation and Formal Techniques

42
References

• Test Generation for Microprocessors S. Thatte et
  al., IEEE Computers, June 1980
• Functional Testing of Microprocessors D. Brahme
  et al., IEEE Computers, 1984
• Automatic Test Program Generation for Pipelined
  Processors H. Iwashita et al., ICCAD 1994
• Architecture Validation for Processors R. Ho et
  al., ISCA 1995
• Automatic Functional Test Program Generation for
  Microprocessors C. Lin et al., DAC 1998
• Micro Architecture Coverage Directed Generation
  of Test Programs S. Ur et al., DAC 1999
• High-Level Test Generation for design
  Verification of Pipelined Microprocessors D.
  Campenhout et al., DAC 1999
• Functional Testing of Microprocessors with Graded
  Fault Coverage R. Kannah et al., ATS 2000
• Instruction Level DFT for Testing Processor and
  IP Cores in System-on-a-Chip W. Lai et al., DAC
  2001
• Automatic Functional Test Program Generation for
  Pipelined Processors using Model Checking, by P.
  Mishra et al., HLDVT 2002.
• A Scalable Software-Based Self-Test Methodology
  for Programmable Processors L. Chen et al., DAC
  2003

43
Thank you !
Thank you !