Design of 4bit ALU

1
Design of 4-bit ALU

• Revati Ingale
• Madhuri Kakulavarapu
• Advisor David W. Parent
• 17th May 2004

2
Agenda

• Abstract
• Introduction
• Why
• Simple Theory
• Back Ground information (Lit Review)
• Summary of Results
• Project (Experimental) Details
• Results
• Cost Analysis
• Conclusions

3
Abstract

• Goal is to design a 4-bit ALU driving up to 30fF.
• Arithmetic operations are AB, AB1, A B, A
  B, Transfer A, Transfer B, A 1, B -1.
• Logical operations are A Ex-OR B, A AND B, A OR
  B, NOT A.
• The data should be transferred at clock rates of
  200 MHz , with 1ns setup and hold times.
• Maximum power is 100mW.
• Maximum area is 500500 µm2

4
Introduction

• Why this project?
• ALU is a building block of several circuits.
• Challenging to design a 16 logic level design
  working at 5ns.
• Challenging to layout.
• Design consists of different kinds of logic Look
  Ahead Carry Generator logic, Full adder,
  Subtractor, Transfer Data, DFF, Super Buffer,
  MUX, Transmission gate, Decoders, Inv, Nand, Nor,
  Ex-Or, etc.

5
Function Table
A, B 4 Bit Input, X dont care
Condition M , S0, S1 Status Control Pin Cin
Carry in Cout Carry Out
6
Block Diagram
Super Buffer
Carry Generator
Subtractor Transfer
Decoder
Adder
Arithmetic Unit
Bank of 9 DFFs
Bank of 5 DFFs
T-gate Based MUX
XOR
AND
OR
INV
MUX-2
Logical Unit
7
Project Summary

• The Look Ahead Carry logic makes the Arithmetic
  unit much faster than the conventional Ripple
  Carry adder.
• The ALU performs Eight Arithmetic functions and
  Four Logical functions at 200MHz.

8
Longest Path Calculation (Arith. Unit)
Note All widths are in microns and capacitances
in fF. Time Delay at complex gate like XOR is bit
more than delay at INV etc.
 
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Schematic Top Level
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D Flip Flop
Decoder
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Arithmetic Unit
12
Look Ahead Carry Generator
2 Select Pin Mux
13
Super Buffer
T gate for Mux
14
Logical Unit
15
Layout
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Verification
17
Simulation-1(Arith.Unit)
M, S1, S0, Cin are set for A-B operation and A3,
A2, A1, A0 are set to 1111.
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Simulation 2 (Logical Unit)
M, S1,S0 are set for XOR operation and
A3,A2,A1,A0 are set to 0110.
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Results

• The ALU performs all 12 functions at a 200Mhz
  clock and a load of 30fF.
• Worst-case Power dissipation is 26.7 mW.
• Area of the layout is 530515µm2.

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Cost Analysis

• Time spent on each phase of the project
• Logic design 1 week.
• Logic check 1 week.
• Gate level design 1 week.
• Integration of schematic blocks 2 weeks.
• Timing check 2 weeks.
• Layout 3 weeks.
• Post extraction check 3 days.

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Summary

• Designed and tested almost all the design units
  that we learnt in the class.
• Designed a 4-Bit ALU that performs eight
  arithmetic and four logical functions at 200MHz
  frequency with setup and hold time 1ns, driving
  up to 30fF.
• This circuit can be used as a building block for
  16/32-bit ALU.
• The Logic design can be modified to perform more
  functions.

22
Acknowledgements

• Thanks to Cadence Design Systems for the VLSI lab
• Thanks to Professor David W. Parent for his
  guidance.