EEL 3705 / 3705L Digital Logic Design

1
EEL 3705 / 3705LDigital Logic Design

• Fall 2006Instructor Dr. Michael FrankModule
  6 Modular Combinational Logic(Thanks to Dr.
  Perry for the slides)

2
Note to Self

• There are still way too many slides in this
  module!
• Need to keep working on making it shorter and
  more concise

3
Wednesday, October 10, 2006

• Administrivia
• This weeks lab
• Finish Top secret code display (w. K-maps),
  finish project
• Design project 1 Due this Friday!!
• Test your designs during a lab period, or in TA
  office hours
• Dont delay writing the large required amount of
  documentation!
• Homework assignment 3
• Due next Monday (October 16th)
• Plan for today
• Show Ping-Pong videogame example, in progress
• See module 99, Designs (v.3) for slides
• Start next lecture topic Modular Combinational
  Logic

4
Modular Combinational Logic

• Original slides by Dr. Reginald Perry
• With modifications additions by Mike Frank

5
Decoders

• General form n-to-2n decoder
• n inputs, 2n outputs
• For each input pattern, one and only one output
  line will be active.
• Uses
• Minterm generator
• Bit/word-line (memory access) circuit
• Code conversion
• Demultiplexing (routing) of data

6
1-to-2 Decoder

• Truth table shown at right
• This one can be implementedby just a simple
  fan-out andan inverter

x y0 y1
0 1 0
1 0 1
y0
y0
x
x
y1
y1
Circuit schematic
Icon
7
Recursive Contruction of n-to-2n Decoder out of
1-to-2 and (n-1)-to-2n-1 Decoders
w0
plus 2n AND gates
w1
w2
xn-1..1
xn-1..0
2n-1 ANDgates
2n-1

n-1
2n
2n-1 ANDgates
z0
x0
z1
8
1-to-2, 2-to-4 and 3-to-8 Decodersusing
recursive design style in Quartus
This is really 4 AND gates in parallel
This is really 8 AND gates in parallel
9
add a slide on the other recursive composition of
2k-to-(2(2k)) decoders
10
2 to 4 Decoder Truth Table

• 2 to 4 decoder

X1 X0 Y0 Y1 Y2 Y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
11
2 to 4 Decoder Equations
12
2 to 4 Decoder Circuit
13
2 to 4 Decoder Block Symbol
Symbol
Circuit
14
3 to 8 Decoder Truth Table
x2 x1 x0 y0 y1 y2 y3 y4 y5 y6 y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
15
3 to 8 Decoder Equations
16
3 to 8 Decoder Circuit
17
3 to 8 Decoder Block Symbol
Symbol
Circuit
18
Design Example

• Using only a 3x8 decoder and two-input OR gates,
  design a logic circuit which implements the
  following Boolean equation

19
Solution
m2
m4
m5
20
2 to 4 Decoder with Enable
21
2x4 Decoder with Enable

• Enable is abbreviated as EN
• EN is called a Control Signal
• Control Signals can be
• Active High Signal
• EN 1 Turns ON Decoder
• Active Low Signal
• EN0 Turns ON Decoder

22
2 x 4 Decoder with Active High Enable Truth
Table
En x1 x0 y3 y2 y1 y0
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
23
2 to 4 Decoder with Enable Equations
24
2 to 4 Decoder with Enable Circuit
25
2 to 4 Decoder with Enable Symbol
26
2 x 4 Decoder with Active High Enable Truth
Table (Short hand notation)
En x1 x0 y3 y2 y1 y0
0 d d 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
d dont care
En has highest priority. If En0, we dont
care about x1 or x0 because Y0
27
2 x 4 Decoder with Active Low Enable Truth
Table (Short hand notation)
EnL x1 x0 y3 y2 y1 y0
1 d d 0 0 0 0
0 0 0 0 0 0 1
0 0 1 0 0 1 0
0 1 0 0 1 0 0
0 1 1 1 0 0 0
d dont care
En has highest priority. If En1, we dont
care about x1 or x0 because Y0
28
2 to 4 Decoder with Active Low Enable Circuit
29
Design Example

• Design a 3x8 decoder using only 2x4 decoders and
  NOT gates.

30
Solution
On when A0
On when A1
31
Encoders

• Opposite of a decoder
• 2n to n encoder
• 2n inputs
• n outputs
• For each input, the circuit will produce an
  encoded output

32
Example 4 to 2 Binary EncoderTruth Table
X3 X2 X1 X0 Y1 Y0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
Assume only one input high at a time!!
33
4 to 2 Encoder Equations
34
Problems with initial design

• Q How do we tell the difference between an input
  of all 0s (i.e. X0) and X1?
• A Add another output (IA) that indicates that
  the input is valid. Lets make IA active low.

35
Problems with initial design

• If IA 1 gt all lines are 0
• If IA 0 gt at least one line is 1
• Q What happens if more than one input is high at
  the same time?
• A Design a priority encoder that will encode
  the input with the highest priority.
• Lets set X3 with the highest priority, followed
  by X2, X1, and X0

36
Example 4 to 2 Priority Binary EncoderTruth
Table
X3 X2 X1 X0 Y1 Y0
0 0 0 1 0 0
0 0 1 d 0 1
0 1 d d 1 0
1 d d d 1 1
37
Solution
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Y1
Y0
38
4 to 2 Priority Encoder Equations
39
Monday, October 16, 2006

• Administrivia
• This weeks lab
• Electronic Device Test PO(2/b), experiment
• Design projects are being graded this week
• Homework assignment 3 is due tonight
• Plan for today
• Finish current topic
• Modular Combinational Logic MUXes, ALUs

40
Multiplexer/Data Selectors

• MUX
• Very Important Module!!!

41
Multiplexer(MUX)/Data Selector

• N to 1 multiplexer (or multiplexor)
• N2k data input lines, D0..(N-1)
• klog2(N) control inputs, S(k-1)..0
• Binary encoding of index of selected data
• One output
• This circuit will connect just the selected
  input to the output.
• The selected input is specified by decoding the
  control inputs.

42
The Simplest Multiplexer

• 2-to-1 multiplexer truth table?
• Output is a copy of
• D0 if S00
• D1 if S01

D0 D1 S0 F
D0 d 0 D0
d D1 1 D1
Schematic,using 1-to-2Decoder module
example 2-to-1 MUX Icon
43
General Construction of a 2k-to-1 MUX from a
k-to-2k decoder, ANDs, and an OR

• This is just a direct generalization of the
  schematic on the previous slide.

F
bussedOR gate
2k
2k
2k
This means 2k ANDgates in parallel
k
S(k-1)..0
44
Recursive Construction of 2k-to-1 muxfrom two
2k-1-to-1 muxes ( a 2-to-1 mux)
2k-1
k-1
F
2k
2k-1
Sk-1
S(k-2)..0
k-1
S(k-1)..0
k
45
4-to-1 MUX from three2-to-1 MUXes

• Try building some larger sizes for yourself

46
Example 4 to 1 MUX Truth Table
Control Inputs
Output
Data Inputs
D0 D1 D2 D3 S1 S0 F
D0 d d d 0 0 D0
d D1 d d 0 1 D1
d d D2 d 1 0 D2
d d d D3 1 1 D3
d dont care / Di data on input i
47
4 to 1 MUX Equation
Ds are the DATA inputs, AB are control inputs
and called the select lines.
48
4 to 1 MUX Circuit
Control Inputs
Data Inputs
Output
2x4 Decoder
Only a single AND gate will be ON at a time.
49
4 to 1 MUX Symbol
A more common, and more mnemonic MUX symbol
D0
Data Inputs
D1
F
Output
D2
Control Inputs
S1..0
D3
50
Logic with multiplexers

• You can implement any n-input logic function with
  a single 2n-to-1 multiplexer, by feeding
  appropriate constants into the MUXs data inputs.
• Namely, the list of the functions output values
  from its truth table
• The multiplexer implements a lookup table
• it simply looks up the function result from the
  indicated row of the truth table
• Of course, this is generally not the most
  hardware-efficient way to implement a given
  function.

51
MUX Application Example

• Using a 4x1 MUX, design a logic circuit which
  implements

We have,
Y
52
Example

• Using a 4x1 MUX, design a logic circuit which
  implements

a b Y Dn
0 0 0 D0
0 1 1 D1
1 0 1 D2
1 1 0 D3
53
Solution
54
Multi-bit Multiplexers

• J-bit nx1 mux

d0
d1
J bits deep
d2
J bits deep
F

dn-1
sel
log2n
j0 to 3
This is just J separate nx1 multiplexers
55
Example 4-bit 4x1 MUX
D03..0
D03..0
D13..0
D13..0
F3..0
F3..0
4 bits deep
D23..0
D23..0
D33..0
D33..0
A B
A
B
j0 to 3
This is just 4 separate 4x1 muxes
56
Example

• 4-bit 4x1 MUX

Bit 0
Bit 1
Bit 2
Bit 3
57
Example 4 bit 4x1 MUX

• For the jth output, we have

D0j
D1j
Fj
D2j
D3j
A
B
58
Example 4 bit 4x1 MUX

• For the bit 0 output, we have

D00
D10
F0
D20
D30
A
B
59
Example 4 bit 4x1 MUX

• For the bit 1 output, we have

D01
D11
F1
D21
D31
A
B
60
Example 4 bit 4x1 MUX

• For the bit 2 output, we have

D02
D12
F2
D22
D32
A
B
61
Example 4 bit 4x1 MUX

• For the bit 3 output, we have

D03
D13
F3
D23
D33
A
B
62
Example 4 bit 4x1 Mux
Complete Circuit
F0
Bit 0
F1
Bit 1
F2
Bit 2
F3
Bit 3
63
Example 4 bit 4x1 MUX

• Symbol

64
Design Example

• Using a 4bit 4x1 MUX, design a 8bit
• 4x1 MUX

65
Solution
66
DeMultiplexers/Data Distributors
67
Demultiplexer/Data Distributor

• Opposite of a multiplexer
• 1 to N demultiplexer
• 1 data input
• N data outputs
• Log2(n) control inputs
• This circuit will connect a data input to one
  and only one output. The selected output is
  specified by a decoding of the control inputs.

68
Example 1 to 4 DeMUX Truth Table
D A B F0 F1 F2 F3
D 0 0 D 0 0 0
D 0 1 0 D 0 0
D 1 0 0 0 D 0
D 1 1 0 0 0 D
d dont care / Di data on input i
69
1 to 4 DeMUX Equations
D is the DATA inputs, AB are control inputs and
called the select lines.
70
1 to 4 DEMUX Circuit
Only one F will be active
2x4 Decoder
Only 1 AND gate will be ON
71
1 to 4 DEMUX Symbol
Selected Lines
Outputs
Data Input
72
Example

• Design a 3x8 decoder using only 2x4 decoders and
  NOT gates.

73
Solution
On when A0
On when A1
74
Basic Arithmetic Elements

• Half Adder

75
Half Adder-Truth Table

• SAB (arithmetic sum)

A B S1 S0
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
76
Half Adder Circuit
77
Full Adder-Truth Table

• SABC (arithmetic sum)

A B C S1 S0
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
78
Full Adder
You can show!!!
79
Synthesis
Logic Equation
Logic Circuit
80
Synthesis
Logic Equation
Logic Circuit
81
Synthesis Full Adder Circuit
A
S(0)
B
C
S(1)
S(0)
S(1)
Simulation
82
Full Adder from Two Half Adders

• Given bits a,b,c, computes (s1s0)2 a b c.
• Can build it using two half adders to compute the
  low-order bit of the sum as s0 (a?b)?c.
• Plus an extra OR gate needed to combine the
  carries.

83
Ripple Carry Adder
84
Conceptualization

• 4-bit adder (worst case)

1
1
1
1111 1111
11110
For the worst case we need to add three bits to
generate a single output bit with a possible
carry out. Can we use our single bit adder for
this?
85
Ripple Carry Adder

• We can cascade several full adders to create a
  ripple carry adder
• The circuit gets its name because the carry bit
  ripples from one bit position to the next

86
Conceptualization
First, lets look at two bits
A(1)
B(1)
Sum(1)
A(0)
B(0)
Sum(0)
What about the carry?
87
Conceptualization
Lets connect the two full adders
A(1)
B(1)
S(1)
Cin
Cout
A(0)
B(0)
S(0)
0
Set carry in for first bit to 0. Why?
88
Analysis
Lets test this for a few cases
0
0
0
Correct!!!
Rule of thumb Always test simple cases first!!
89
Analysis
Lets test this for the a few cases
1
1
1
Correct!!!
90
Analysis
Lets test this for the a few cases
0
0
0
1
1
1
1
1
0
0
Correct!!!
91
Four Bit Ripple Adder
Carry out
Carry in
92
8-bit Ripple Carry Adder

• Use two 4-bit adders

93
16-bit Ripple Carry Adder

• Use two 8-bit adders

94
Subtraction Circuit
95
Subtraction Circuit

• Calculate 2s complement of B
• Add B to A

96
Add/Sub Circuit
97
Add/Sub Circuit Module
98
Function Table for Add/Sub Module
Add Functional Result
0 SAB
1 SA-B
Add is a control input. It is active low. This
means that the module will compute AB when
Add0. It will compute A-B when Add1.
99
Add/Sub Circuit

• Design using Modules

100
Add/Sub Circuit
101
Add/Sub Circuit
Add operation. Add0
0
0
102
Add/Sub Circuit
Sub operation. Add1
1
1
103
Wednesday, October 18, 2006

• Administrivia
• This weeks lab
• Electronic Device Test PO(2/b), experiment
• Next weeks lab
• Midterm Practical Exam
• Design projects are being graded this week
• Homework assignment 4 will be out soon!
• Plan for today
• Finish current topic
• Modular Combinational Logic Comparators, ALUs

104
Comparators
105
Equal Comparator

• Design a logic circuit which will compute
• F0 (A B)

106
2-bit Equal Comparator Truth Table
b1 b0 a1 a0 F0
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
107
2-bit Equal Comparator Truth Table
b1 b0 a1 a0 F0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
108
Solution
You can show,
109
N-bit Equal Comparator
110
Not Equal Comparator

• Design a logic circuit which will compute
• F (A ltgt B)

F (A B)
i.e. Just invert our Equal Comparator circuit
111
Magnitude Comparator

• Design a logic circuit which will compute
• F2 (AgtB)
• F1 (AltB)

Lets develop a truth table for 2-bits
112
2-bit Magnitude (unsigned) Comparator Truth Table
b1 b0 a1 a0 F2 F1
0 0 0 0 0 0
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 1 0
0 1 0 0 0 1
0 1 0 1 0 0
0 1 1 0 1 0
0 1 1 1 1 0
113
2-bit Magnitude (unsigned) Comparator Truth Table
b1 b0 a1 a0 F2 F1
1 0 0 0 0 1
1 0 0 1 0 1
1 0 1 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 0 1 0 1
1 1 1 0 0 1
1 1 1 1 0 0
114
You can show
115
Arithmetic Logic Units (ALUs)
116
Arithmetic Logic Unit (ALU)
A,B are data inputs of n bits each in depth S is
a control input. We have 2m operations F is the
output
117
Example

• Let n4,m3
• We have A3..0 and B3..0
• With m3, we have 23 8 operations
• Lets look at a possible function table

118
Function Table
s2 s1 s0 Function
0 0 0 FAB
0 0 1 FAB (logical OR)
0 1 0 FNOT A
0 1 1 FA XOR B
1 0 0 FAB (Arithmetic)
1 0 1 FA-B
1 1 0 FA 1
1 1 1 FA - 1
119
Design using a Truth Table

• How large is the truth table?
• 2n from data inputs A and B
• Example n8, we have 16 data inputs
• A7..0 and B7..0
• 3 control inputs
• Total of 2n3 inputs
• N8, we have 19 inputs
• Our truth table will have
• 192 (361) rows and 8 outputs
• Too complex. Lets explore another alternative
  using a system or modular approach

120
Design using Modules

• Note
• For S20, we have logic operations
• For S21, we have arithmetic operations
• So, lets use S2 to control a 2x1 MUX
• to select between logic and arithmetic
  operations, so our top level design would look
  like

121
ALU Design
122
ALU Design S20
With S20, F is the output from the logic module
123
ALU Design S21
With S21, F is the output from the arithmetic
module
124
Logic Module Design
125
Function Table for Logic Module

• S20

s2 s1 s0 Function
0 0 0 FAB
0 0 1 FAB (logical OR)
0 1 0 FNOT A
0 1 1 FA XOR B
We can use a 4x1 mux to implement this module
126
Logic Module Design
127
Logic Module Design
FAB
AND Operation S1..000
0 0
128
Logic Module Design
FAB
OR Operation S1..001
0 1
129
Logic Module Design
FA
NOT Operation S1..010
1 0
130
Logic Module Design
FA XOR B
XOR Operation S1..011
1 1
131
What do these logic moduleslook like?
132
AND Module
133
OR Module
134
NOT Module
A
F
135
XOR Module
136
Arithmetic Module

• Lets use our ADD/SUB Module

137
Add/Sub Circuit Module
138
Function Table for Arithmetic Ops
s2 s1 s0 Function
1 0 0 FAB (Arithmetic)
1 0 1 FA-B
1 1 0 FA 1
1 1 1 FA - 1
Note S0 can be use to indicate Addition or
Subtraction. S1 can be use to indicate the B data
input
139
Arithmetic Module Design
140
Arithmetic Module Design
FAB
S1..000
0
0
141
Arithmetic Module Design
FA-B
S1..001
1
0
142
Arithmetic Module Design
FA1
S1..010
0
1
143
Arithmetic Module Design
FA-1
S1..011
1
1
144
Overall Design

• We have

145
ALU Design
146
Logic Module Design
147
Arithmetic Module Design
148
Total Design
Logic Module
Arithmetic Module
149
End of Chapter 4